 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
LE25S161 Datasheet(PDF) 15 Page - ON Semiconductor |
|
|
|||||||||||||||||||||||||||||
LE25S161 Datasheet(HTML) 15 Page - ON Semiconductor |
|
|
15 / 54 page  LE25S161 www.onsemi.com 15 9-1-4. SUS (bit 6) The SUS register indicates when Erase/Program operation has been suspended. The SUS becomes "1" when the Erase/Program operation has been suspended (WSUS: B0h). The SUS is cleared to"0" by Resume (RESM:30h) or re-erase/program (SSE, SE, CHE, PP, PPL). 9-1-5. SRWP (bit 7) Write Status Register protect SRWP is the bit for protecting the status registers, and its information can be rewritten. When SRWP is "1" and the logic level of the WP pin is low, the Write Status Register (WRSR: 01h) is ignored, and status registers BP0, BP1, BP2, TB and SRWP are protected. When the logic level of the WP pin is high, the status registers are not protected regardless of the SRWP state. The SRWP setting conditions are shown in "Table 5. SRWP Setting Conditions". Table 5. SRWP Setting Conditions WP Pin SRWP Status Register Protect State 0 0 Unprotected 1 Protected 1 0 Unprotected 1 Unprotected |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
