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PM5347 Datasheet(PDF) 229 Page - PMC-Sierra, Inc |
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PM5347 Datasheet(HTML) 229 Page - PMC-Sierra, Inc |
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229 / 302 page ![]() PM5347 S/UNI-PLUS DATA SHEET PMC-941033 ISSUE 6 SATURN USER NETWORK INTERFACE PLUS PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 213 drive the data bus and holding the CSB pin low tri-states the data bus. The DBCTRL bit overrides the HIZDATA bit. The DBCTRL bit is used to measure the drive capability of the data bus driver pads. PMCTST: The PMCTST bit is used to configure the digital portion of the S/UNI-PLUS for PMC's manufacturing tests. When PMCTST is set to logic one, the S/UNI-PLUS microprocessor port becomes the test access port used to run the PMC manufacturing test vectors. The PMCTST bit is logically "ORed" with the IOTST bit, and can be cleared by setting CSB to logic one or by writing logic zero to the bit. PMCATST: The PMCATST bit is used to configure the analog portion of the S/UNI-PLUS for PMC's manufacturing tests. When PMCATST is set to logic one, the S/UNI-PLUS microprocessor port becomes the test access port used to run the PMC manufacturing analog test vectors. The PMCATST bit is logically "ORed" with the IOTST bit, and can be cleared by setting CSB to logic one or by writing logic zero to the bit. TT_BYP: The TT_BYP bit is used to bypass the glue logic on the TTOH and TTOHEN input pins to permit direct access to the TTOP block. When TT_BYP is set to logic one, the glue logic is bypassed, and TTOH and TTOHEN feed directly into the TTOP block. When TT_BYP is set to logic zero, the glue logic is not bypassed, and TTOH and TTOHEN pass through the glue logic before entering the TTOP block. 11.2 Test Mode 0 Details In test mode 0, the S/UNI-PLUS allows the logic levels on the device inputs to be read through the microprocessor interface, and allows the device outputs to be forced to either logic level through the microprocessor interface. The IOTST bit in the Master Test register should be set to logic one. To enable test mode 0, the IOTST bit in the Master Test register is set to logic one and the following addresses must be written with 00H: 91H, 95H, 99H, A1H, A5H, A7H, A9H, B1H, C1H, D1H, E1H, E9H, F1H. Clock edges must be provided on inputs TFCLK and RFCLK. |
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