PM5347 datasheet(243/302 Pages) PMC

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PM5347 S/UNI-PLUS

DATA SHEET

PMC-941033

ISSUE 6

SATURN USER NETWORK INTERFACE PLUS

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

227

The 8-bit SCI-PHY compliant data structure is selected when the BUS8 input is

tied high. Bit 7 of each word is the most significant bit (which corresponds to the

first bit transmitted or received). The header check sequence octet (HCS) is

passed through this structure. The start of cell indication input and output (TSOC

and RSOC) are coincident with Word 1 (containing the first cell header octet).

Word 5 of this structure contains the HCS octet.

In the receive direction, cells containing "detected and uncorrected" header

errors are dropped when the HCSPASS bit in the RACP Control/Status Register

is set to logic zero. No HCS status information is passed within this data

structure. Error free headers and "detected and corrected" headers are passed

when HCSPASS is a logic zero. Error free headers, "detected and corrected"

headers, and "detected and uncorrected" headers are passed when HCSPASS

is a logic one.

In the transmit direction, the HCS bit in the TACP Control Register determines

whether the HCS is calculated internally or is inserted directly from Word 5.

12.7

Bit Error Rate Monitor

The S/UNI-PLUS Bit Error Rate Monitor (BERM) block counts line BIP errors

over programmable periods of time and monitors whether the accumulated count

of line BIP errors exceeds a programmable threshold within that specific period.

The BERM block can be used to trigger an interrupt when the bit error rate (BER)

of the line is ±50% of the programmed rate. The following tables list the

recommended contents of the BERM Line BIP Accumulation Period and BERM

Line BIP Threshold Period registers to detect various BERs.

In STS-1 mode, the following register contents are recommended:

Table 8

BER

Accumulation

Period LSB

Accumulation

Period MSB

Threshold

LSB

Threshold

MSB

10-4

0x87

0x01

0xCA

0x00

10-5

0x19

0x0F

0xD9

0x00

10-6

0xFA

0x9C

0xDB

0x00

In STS-3c mode, the following register contents are recommended:

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