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S39421 Datasheet(PDF) 1 Page - Summit Microelectronics, Inc. |
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S39421 Datasheet(HTML) 1 Page - Summit Microelectronics, Inc. |
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1 / 28 page  1 © SUMMIT MICROELECTRONICS, Inc. 1999 2024 9.0 8/8/00 Characteristics subject to change without notice SUMMIT MICROELECTRONICS, Inc. SUMMIT MICROELECTRONICS, Inc. • 300 Orchard City Drive, Suite 131 • Campbell, CA 95008 • Telephone 408-378-6461 • Fax 408-378-6586 • www.summitmicro.com FEATURES • Full Voltage Control for Hot Swap Applications – Card Insertion Detection – Platform Voltage Detection – Card Voltage Sequencing – 5 Volt, 12 Volt and 3.3 Volt • 12 Volt FET Enable Outputs – Allows use of Low On-resistance N-Channel FETS • Card Reset Generation Based on Out of Spec Voltages – Host Reset • Programmable Slew Rate Control [250V/Sec Default Rate] • Supports 5 Volt, 3.3 Volt and Mixed Voltage Cards • Integrated 1K Bit E2PROM Memory • Data Download™ Mode [Simplifies Downloading of Configuration Memory into Interface ASIC or MCU] Hot Swap Voltage Controller S39421 DESCRIPTION The S39421 is a fully integrated hot swap controller intended for use on add-in cards that may be inserted into or removed from powered-on host platforms. The S39421 performs a variety of tasks starting with the validation of proper card insertion and the presence of “in-spec” volt- ages at the host platform interface. Once power is switched on, the S39421 continues to monitor the back-end power to the add-in card and the host power supply. If either the 5V or 3.3V supplies drop below Vtrip the S39421 will immediately assert the RE- SET outputs and power-down the add-in card. In addition to the power control for the add-in card, the S39421 provides status signals that can be employed by the host and for the control of bus interface components. The on board E2PROM can be used as configuration memory for the individual card or as general purpose memory. The proprietary DataDownload mode provides a more direct interface to the E2PROM for simplified access by the add-in card’s controller or ASIC. FUNCTIONAL BLOCK DIAGRAM + + - - EEPROM Memory Array Slew Rate Control VGATE3 VGATE5 CS SK DI DO CARD_3V CARD_5V + - + - ISLEW PND1 PND2 DRVREN SGNL_VLD RESET RESET VCC5 VCC3 DD Filter RESET Timer Sequencing Logic 2024 ILL2.1 CARD_V_VLD ASSOCIATE MEMBER |
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