S39421 datasheet(23/28 Pages) SUMMIT

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S39421

2024 9.0 8/8/00

The S39421 will now begin monitoring the backend circuit

voltages and when they are at or above Vtrip the reset

timer will be released to begin the time out period and

CARD_V_VLD will be released. After tPURST has ex-

pired, the reset outputs will be released and SGNL_VLD

will be driven active. The SGNL_VLD signal can be tied to

the host LI/O* signal pin to indicate the card has been fully

powered, cleanly reset and is ready for action.

Backplane/Add-in Card Sequencing

A more complicated problem than the sequencing shown

above is the signal bus interface. Inserting unpowered

circuits onto the signal bus could lead to a situation of

damaging components and much more likely disrupting

the signals on the backplane. This will involve a rigorous

evaluation and selection process by the design engineer

to determine the best solution for the individual applica-

tion. However, we can examine a product family that

should resolve most of the issues the designer might

encounter. The proposed VME Live Insertion spec actu-

ally helps us narrow this down quickly by recommending

the use of ABTE logic. This is available from at least two

large manufacturers of semiconductors.

Avoidance of Bus Conflicts

Bus conflicts arise when two or more interface circuits

attempt to drive the bus simultaneously with one circuit

driving high and the other driving low. The device trying to

drive low will most likely not incur damage. But the device

trying to drive high will be dropping 5Volts on its output at

up to 120mA current. Even for very short periods of time

the high temperatures this will generate can either destroy

the device or adversely affect the long-term reliability of

the device. The best solution is to insure the transceiver’s

enable input is actively driven before the transceiver is

powered-on. Using one of the reset outputs (as shown in

figure 27) as a gating signal to a single enable input style

transceiver is one solution. With a dual enable transceiver

one of the reset outputs can be tied directly to appropriate

enable input.

FIGURE 26: BACKEND VOLTAGE CONTROL CIRCUIT

-12V

+12V

+3.3V

+5V

Gnd

Vpc

Gnd

Vpc

VCC5

CARD_3V

CARD_5V

+5V

+3.3V

-12V

+12V

S39421

2024 ILL29.3

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