S39421 datasheet(11/28 Pages) SUMMIT

11 / 28 page

S39421

2024 9.0 8/8/00

FIGURE 6. READ INSTRUCTION TIMING

2024 ILL20.0

tCS

STANDBY

tHZ

HIGH-Z

AN–1

DN DN–1

tPD0

Erase/Write Enable and Disable

The memory powers up in the write disable state. Any

writing after power-up or after an EWDS (write disable)

instruction must first be preceded by the EWEN (write

enable) instruction. Once the write instruction is enabled,

it will remain enabled until power to the device is removed,

or the EWDS instruction is sent. The EWDS instruction

can be used to disable all S39421 write and clear instruc-

tions, and will prevent any accidental writing or clearing of

the device. Data can be read normally from the device

regardless of the write enable/disable status.

Write All

Upon receiving a WRAL command and data, the CS (Chip

Select) pin must be deselected for a minimum of 250ns

(tCSMIN). The falling edge of CS will start the self clocking

data write to all memory locations in the device. The

clocking of the SK pin is not necessary after the device has

entered the self clocking mode. The ready/busy status of

the S39421 can be determined by selecting the device

and polling the DO pin. It is not necessary for all memory

locations to be cleared before the WRAL command is

executed.

FIGURE 7. WRITE INSTRUCTION TIMING

2024 ILL21.0

tCS

STANDBY

HIGH-Z

101

AN-1

BUSY

READY

STATUS

VERIFY

tSV

tHZ

tEW

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