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AM79C970 Datasheet(PDF) 26 Page - Advanced Micro Devices |
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AM79C970 Datasheet(HTML) 26 Page - Advanced Micro Devices |
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26 / 168 page  P R E L I M I N A R Y AMD 1-893 Am79C970 Basic Burst Write Cycles The PCnet-PCI controller provides a burst mode to write data to the receive buffer. The burst mode must be en- abled by setting BWRITE in BCR18. All PCnet-PCI con- troller burst write transfers are of the PCI command type Memory Write (type 7). AD[1:0] will both be ZERO dur- ing the address phase indicating a linear burst order. All four byte enable signals will be ZERO during the data phase as the PCnet-PCI controller always writes a full 32-bit word when in burst mode. Figure 6 shows a typical burst write access. The PCnet- PCI controller arbitrates for the bus, is granted access, and writes four 32-bit words (DWORDs) from system memory and then releases the bus. In this example, the memory system extends the data phase of the first ac- cess by one wait state. The following three data phases take one clock cycle each, which is determined by the timing of TRDY. 18220C-8 FRAME CLK AD IRDY TRDY C/ BE DEVSEL REQ GNT 12345678 ADDR DATA DATA DATA 0000 0111 10 9 PAR PAR PAR PAR PAR DEVSEL is sampled by the PCnet-PCI controller. DATA PAR Figure 6. Burst Write Cycles |
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