AM79C970 datasheet(50/168 Pages) AMD

50 / 168 page

P R E L I M I N A R Y

AMD

1-917

Am79C970

If the OWN bit is set and the buffer length is 0, the OWN

bit will be reset. In the LANCE the buffer length of 0 is

interpreted as a 4096-byte buffer. It is acceptable to

have a 0 length buffer on transmit with STP = 1 or

STP=1

and ENP = 1. It is not acceptable to have 0

length buffer with STP = 0 and ENP =1.

If the OWN bit is set and the start of frame (STP) bit is

set, then microcode control proceeds to a routine that

will enable transmit data transfers to the FIFO. The

PCnet-PCI controller will look ahead to the next transmit

descriptor after it has performed at least one transmit

data transfer from the first buffer. (More than one trans-

mit data transfer may possibly take place, depending

upon the state of the transmitter.) The contents of TMD0

and TMD1 will be stored in Next Xmt Buffer Address

(CSR64 and CSR65), Next Xmt Byte Count (CSR66)

and Next Xmt Status (CSR67) regardless of the state of

the OWN bit. This transmit descriptor lookahead opera-

tion is performed only once.

If the PCnet-PCI controller does not own the next TDTE

(i.e. the second TDTE for this frame), then it will com-

plete transmission of the current buffer and then update

the status of the current (first) TDTE with the BUFF and

UFLO bits being set. This will cause the transmitter to be

disabled (CSR0, TXON=0). The PCnet-PCI controller

will have to be re-initialized to restore the transmit func-

tion. The situation that matches this description implies

that the system has not been able to stay ahead of the

PCnet-PCI controller in the transmit descriptor ring and

therefore, the condition is treated as a fatal error. (To

avoid this situation, the system should always set the

transmit chain descriptor own bits in reverse order.)

If the PCnet-PCI controller does own the second TDTE

in a chain, it will gradually empty the contents of the first

buffer (as the bytes are needed by the transmit opera-

tion), perform a single-cycle DMA transfer to update the

status of the first descriptor (reset the OWN bit in

TMD1), and then it may perform one data DMA access

on the second buffer in the chain before executing an-

other lookahead operation. (i.e. a lookahead to the third

descriptor.)

The PCnet-PCI controller can queue up to two frames in

the transmit FIFO. Call them frame “X” and frame “Y”,

where “Y” is after “X”. Assume that frame “X” is currently

being transmitted. Because the PCnet-PCI controller

can perform lookahead data transfer past the ENP of

frame “X”, it is possible for the PCnet-PCI controller to

completely transfer the data from a buffer belonging to

frame “Y” into the FIFO even though frame “X” has not

yet been completely transmitted. At the end of this “Y”

buffer data transfer, the PCnet-PCI controller will write

intermediate status (change the OWN bit to a ZERO) for

the “Y” frame buffer, if frame “Y” uses data chaining.

The last TDTE for the “X” frame (containing ENP) has

not yet been written, since the “X” frame has not yet

been completely transmitted. Note that the PCnet-PCI

controller has, in this instance, returned ownership of a

TDTE to the host out of a “normal” sequence.

For this reason, it becomes imperative that the host sys-

tem should never read the Transmit DTE ownership bits

out of order. Software should always process buffers in

sequence, waiting for the ownership before proceeding.

There should be no problems for software which proc-

esses buffers in sequence, waiting for ownership before

proceeding.

If an error occurs in the transmission before all of the

bytes of the current buffer have been transferred, then

TMD2 and TMD1 of the current buffer will be written; In

such a case, data transfers from the next buffer will not

commence. Instead, following the TMD2/TMD1 update,

the PCnet-PCI controller will go to the next transmit

frame, if any, skipping over the rest of the frame which

experienced an error, including chained buffers. This is

done by returning to the polling microcode where

PCnet-PCI controller will immediately access the next

descriptor and find the condition OWN=1 and STP=0 as

described earlier. As described for that case, the PCnet-

PCI controller will reset the own bit for this descriptor

and continue in like manner until a descriptor with

OWN=0 (no more transmit frames in the ring) or

OWN=1 and STP=1 (the first buffer of a new frame)

is reached.

At the end of any transmit operation, whether successful

or with errors, immediately following the completion of

the descriptor updates, the PCnet-PCI controller will al-

ways perform another poll operation. As described ear-

lier, this poll operation will begin with a check of the

current RDTE, unless the PCnet-PCI controller already

owns that descriptor. Then the PCnet-PCI controller will

proceed to polling the next TDTE. If the transmit descrip-

tor OWN bit has a ZERO value, then the PCnet-PCI con-

troller will resume poll time count incrementing. If the

transmit descriptor OWN bit has a value of ONE, then

the PCnet-PCI controller will begin filling the FIFO with

transmit data and initiate a transmission. This end–of–

operation poll coupled with the TDTE lookahead opera-

tion allows the PCnet-PCI controller to avoid inserting

poll time counts between successive transmit frames.

Whenever the PCnet-PCI controller completes a trans-

mit frame (either with or without error) and writes the

status information to the current descriptor, then the

TINT bit of CSR0 is set to indicate the completion of a

transmission. This causes an interrupt signal if the IENA

bit of CSR0 has been set and the TINTM bit of CSR3

is reset.

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