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AM79C970 Datasheet(PDF) 78 Page - Advanced Micro Devices

Part # AM79C970
Description  PCnetTM-PCI Single-Chip Ethernet Controller for PCI Local Bus
PDF  168 Pages
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Manufacturer  AMD [Advanced Micro Devices]
Direct Link  http://www.amd.com
Logo AMD - Advanced Micro Devices

AM79C970 Datasheet(HTML) 78 Page - Advanced Micro Devices

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P R E L I M I N A R Y
AMD
1-945
Am79C970
Pin 120 (
RST) is the first input to the NAND tree. Pin 117
(
INTA) is the second input to the NAND tree, followed by
pin 121 (CLK). All other PCI bus signals follow, counter-
clockwise, with pin 57 (AD0) being the last. Pins labeled
NC and all power supply pins are not part of the NAND
tree. Table 9 shows the complete list of pins connected
to the NAND tree.
Table 9. NAND Tree Configuration
NAND
NAND
NAND
Tree
Tree
Tree
Input #
Pin #
Name
Input #
Pin #
Name
Input #
Pin #
Name
1
120
RST
18
15
AD21
35
36
AD15
2
117
INTA
19
16
AD20
36
38
AD14
3
121
CLK
20
18
AD19
37
39
AD13
4
123
GNT
21
19
AD18
38
40
AD12
5
126
REQ
22
21
AD17
39
41
AD11
6
128
AD31
23
22
AD16
40
42
AD10
7
129
AD30
24
23
C/
BE2
41
44
AD9
8
131
AD29
25
24
FRAME
42
45
AD8
9
132
AD28
26
25
IRDY
43
47
C/
BE0
10
2
AD27
27
26
TRDY
44
48
AD7
11
3
AD26
28
27
DEVSEL
45
49
AD6
12
5
AD25
29
28
STOP
46
51
AD5
13
6
AD24
30
29
LOCK
47
52
AD4
14
7
C/
BE331
31
PERR
48
53
AD3
15
10
IDSEL
32
32
SERR
49
54
AD2
16
12
AD23
33
34
PAR
50
56
AD1
17
13
AD22
34
35
C/
BE1
51
57
AD0
RST must be asserted low to start a NAND tree test se-
quence. Initially, all NAND tree inputs except
RST
should be driven high. This will result in a high output at
the NOUT pin. If the NAND tree inputs are driven from
high to low in the same order as they are connected to
build the NAND tree, NOUT will toggle every time an ad-
ditional input is driven low. NOUT will change to a
ZERO, when
INTA is driven low and all other NAND tree
inputs stay high. NOUT will toggle back to high, when
CLK is additionally driven low. The square wave will
continue until all NAND tree inputs are driven low.
NOUT will be high, when all NAND tree inputs are
driven low.
Note that some of the pins connected to the NAND tree
are outputs in normal mode of operation. They must not
be driven from an external source until the PCnet-PCI
controller is configured for NAND tree testing.



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