AM79C970 datasheet(100/168 Pages) AMD

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P R E L I M I N A R Y

AMD

1-967

Am79C970

CSR46: Poll Time Counter

Bit

Name

Description

31–16

RES

Reserved locations. Written as

ZEROs and read as undefined.

15–0

POLL

Poll Time Counter. This counter

is incremented by the PCnet-PCI

controller microcode and is used

to trigger the descriptor ring poll-

ing operation of the PCnet-PCI

controller.

Read/write accessible only when

STOP bit is set. These bits are

unaffected

H_RESET,

S_RESET or STOP.

CSR47: Polling Interval

Bit

Name

Description

31–16

RES

Reserved locations. Written as

ZEROs and read as undefined.

15–0 POLLINT

Polling Interval. This register

contains the time that the PCnet-

PCI controller will wait between

successive polling operations.

The POLLINT value is expressed

as the twos complement of the

desired interval, where each bit

of POLLINT represents 1 CLK

period of time. POLLINT[3:0] are

ignored.

(POLLINT[16] is im-

plied to be a one, so POL-

LINT[15] is significant, and does

not represent the sign of the twos

complement POLLINT value.)

The default value of this register

is 0000b. This corresponds to a

polling interval of 65,536 clock

periods (1.966 ms when CLK =

33 MHz). The POLLINT value of

0000b is created during the

microcode initialization routine,

and therefore might not be seen

when

reading

CSR47

after

H_RESET or S_RESET.

If the user desires to program a

value for POLLINT other than the

default, then the correct proce-

dure is to first set INIT only in

CSR0. Then, when the initializa-

tion sequence is complete, the

user must set STOP in CSR0.

Then the user may write to

CSR47 and then set STRT in

CSR0. In this way, the default

value of 0000b in CSR47 will be

overwritten with the desired user

value.

If the user does NOT use the

standard initialization procedure

(standard implies use of an in-

itialization block in memory and

setting the INIT bit of CSR0), but

instead, chooses to write directly

to each of the registers that are

involved in the INIT operation,

then it is imperative that the user

also write 0000 0000 to CSR47

as part of the alternative initiali-

zation sequence.

Read/write accessible only when

STOP bit is set. These bits are

unaffected

H_RESET,

S_RESET or STOP.

CSR58: Software Style

Bit

Name

Description

This register is an alias of the lo-

cation BCR20. Accesses to/from

this register are equivalent to ac-

cesses to BCR20.

31–16

RES

Reserved locations. Written as

ZEROs and read as undefined.

15–10

RES

Reserved locations. Written as

ZEROs and read as undefined.

CSRPCNET

CSR PCnet-ISA configuration

bit. When set, this bit indicates

that the PCnet-PCI controller

will map directly to the CSR4 and

CSR3 bits of the PCnet–ISA

(Am79C960)

device.

When

cleared, this bit indicates that

PCnet-PCI controller register bits

of CSR4 and CSR3 will map di-

rectly to the CSR4 and CSR3 bits

the

ILACC

(Am79C900)

device.

The value of CSRPCNET is de-

termined by the PCnet-PCI con-

troller. CSRPCNET is read only

by the host.

The PCnet-PCI controller uses

the setting of the Software Style

bits 7–0) to determine the value

for this bit.

CSRPCNET is set by H_RESET

and is not affected by S_RESET

or STOP.

SSIZE32

Software Size 32 bits. When set,

this bit indicates that the PCnet-

PCI

controller

utilizes

Am79C900

(ILACC)

software

structures.

particular,

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