AM79C970 datasheet(40/168 Pages) AMD

40 / 168 page

P R E L I M I N A R Y

AMD

1-907

Am79C970

Partial Linear Burst

Certain factors may cause the PCnet-PCI controller to

burst fewer than the LINBC limit during a single burst se-

quence. Factors that could generate a partial linear

burst include:

No more data available for transfers from the

current TX buffer

No more data available for transfer from the RX

FIFO for this packet

No more space available for transfers to the

current RX buffer

Preemption

Typically, during the case of a master read operation (for

TX buffer transfers), the last transfer in the linear burst

sequence will be the last transfer executed before the

PCnet-PCI controller releases the bus. This is true of

both partial and completed linear burst sequences.

During the case of a master write operation (for RX

buffer transfers) when RX packet data has ended, the

last transfer in the linear burst sequence will be the last

transfer executed before the PCnet-PCI controller re-

leases the bus. This is true of both partial and completed

linear burst sequences.

However, if the next transfer that the PCnet-PCI control-

ler is scheduled to execute will be to the last available

location of a RX buffer, then the PCnet-PCI controller

will use a non-burst cycle to make the last transfer to the

buffer. This event occurs because of the restrictions

placed upon the byte enable signals during the linear

burst operation. As mentioned in the initial description of

linear burst accesses, all byte lanes of the data bus are

always enabled during linear burst operations. Note,

however, that in the case of the last RX buffer location,

the PCnet-PCI controller may own only a portion of the

DWORD location. In such cases, it is necessary to dis-

continue linear burst accesses on the second from last

RX buffer location so that an ordinary transfer with some

byte lanes disabled can be used for the final transfer.

AM79C970 Datasheet(PDF) 40 Page - Advanced Micro Devices

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