AM79C970 datasheet(75/168 Pages) AMD

75 / 168 page

AMD

P R E L I M I N A R Y

1-942

Am79C970

back mode, data can be transmitted to and received

from the external network.

There are restrictions on loopback operation. The

PCnet-PCI controller has only one FCS generator cir-

cuit. The FCS generator can be used by the transmitter

to generate the FCS to append to the frame, or it can be

used by the receiver to verify the FCS of the received

frame. It can not be used by the receiver and transmitter

simultaneously.

If the FCS generator is connected to the receiver, the

transmitter will not append an FCS to the frame, but the

receiver will check for one. The user can, however, cal-

culate the FCS value for a frame and include this four-

byte number in the transmit buffer.

If the FCS generator is connected to the transmitter, the

transmitter will append an FCS to the frame, but the re-

ceiver will not check for the FCS. However, the user can

verify the FCS by software.

During loopback, the FCS logic can be allocated to the

receiver by setting DXMTFCS = 1 in CSR15.

If DXMTFCS=0, the MAC Engine will calculate and ap-

pend the FCS to the transmitted message. The receive

message passed to the host will therefore contain an ad-

ditional 4 bytes of FCS. In this loopback configuration,

the receive circuitry cannot detect FCS errors if

they occur.

If DXMTFCS=1, the last four bytes of the transmit mes-

sage must contain the (software generated) FCS com-

puted for the transmit data preceding it. The MAC

Engine will transmit the data without addition of an FCS

field, and the FCS will be calculated and verified at

the receiver.

The loopback facilities of the MAC Engine allow full op-

eration to be verified without disturbance to the network.

Loopback operation is also affected by the state of the

Loopback Control bits (LOOP, MENDECL, and INTL) in

CSR15. This affects whether the internal MENDEC is

considered

part

the

internal

external

loopback path.

The multicast address detection logic uses the FCS

generator circuit. Therefore, in the loopback mode(s),

the multicast address detection feature of the MAC En-

gine, programmed by the contents of the Logical Ad-

dress Filter (LADRF [63:0] in CSRs 8–11) can only be

tested when DXMTFCS=1, allocating the FCS genera-

tor to the receiver. All other features operate identically

in loopback as in normal operation, such as automatic

transmit padding and receive pad stripping.

When performing an internal loopback, no frame will be

transmitted to the network. However, when the PCnet-

PCI controller is configured for internal loopback the re-

ceiver will not be able to detect network traffic. External

loopback tests will transmit frames onto the network if

the AUI port is selected, and the PCnet-PCI controller

will receive network traffic while configured for external

loopback when the AUI port is selected. Runt Packet

Accept is automatically enabled when any loopback

mode is invoked.

Loopback mode can be performed with any frame size.

Runt Packet Accept is internally enabled (RPA bit in

CSR124 is not affected) when any loopback mode is in-

voked. This is to be backwards compatible to the

LANCE (Am7990) software.

When the 10BASE-T MAU is selected in external loop-

back mode, the collision detection is disabled. This is

necessary, because a collision in a 10BASE-T system is

defined as activity on the transmitter outputs and re-

ceiver inputs at the same time, which is exactly what oc-

curs during external loopback.

Since a 10BASE-T hub does not normally feed the sta-

tion’s transmitter outputs back into the station’s receiver

inputs, the use of external loopback in a 10BASE-T sys-

tem usually requires some sort of external hardware that

connects the outputs of the 10BASE-T MAU to

its inputs.

LED Support

The PCnet-PCI controller can support up to 3 LEDs.

LED outputs

LNKST and LED1 allow for direct connec-

tion of an LED and its supporting pullup device. LED out-

put

LED3 may require an additional buffer between the

PCnet-PCI controller output pin and the LED and its

supporting pullup device.

Because the

LED3 output is multiplexed with other

PCnet-PCI controller functions, it may not always be

possible to connect an LED circuit directly to the

LED3

pin. For example, when an LED circuit is directly con-

nected to the EEDO/

LED3 pin, then it is not possible for

most serial EEPROM devices to sink enough IOL to

maintain a valid low level on the EEDO input to the

PCnet-PCI controller. Therefore, in applications that re-

quire both an EEPROM and a third LED, then it is neces-

sary

buffer

the

LED3

circuit

from

the

EEPROM-PCnet-PCI connection. The LED registers in

the BCR resource space allow each LED output to be

programmed for either active high or active low opera-

tion, so that both inverting and non-inverting buffering

choices are possible.

In applications where an EEPROM is not needed, the

LED3 pin may be directly connected to an LED circuit.

The PCnet-PCI

LED3 pin driver will be able to sink

enough current to properly drive the LED circuit.

By default, after H_RESET, the 3 LED outputs are con-

figured in the following manner:

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