AM79C970 datasheet(53/168 Pages) AMD

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AMD

P R E L I M I N A R Y

1-920

Am79C970

The status of each receive message is available in the

appropriate RMD and CSR areas. FCS and Framing er-

rors (FRAM) are reported, although the received frame

is still passed to the host. The FRAM error will only be

reported if an FCS error is detected and there are a non

integral number of bytes in the message. The MAC en-

gine will ignore up to 7 additional bits at the end of a mes-

sage (dribbling bits), which can occur under normal

network operating conditions. The reception of 8 addi-

tional bits will cause the MAC engine to de-serialize the

entire byte, and will result in the received message and

FCS being modified.

The PCnet-PCI controller can handle up to 7 dribbling

bits when a received frame terminates. During the re-

ception, the FCS is generated on every serial bit (includ-

ing the dribbling bits) coming from the cable, although

the internally saved FCS value is only updated on the

eighth bit (on each byte boundary). The framing error is

reported to the user as follows:

If the number of dribbling bits are 1 to 7 and there

is no CRC (FCS) error, then there is no Framing

error (FRAM = 0).

If the number of dribbling bits are 1 to 7 and there

is a CRC (FCS) error, then there is also a Framing

error (FRAM = 1).

If the number of dribbling bits = 0, then there is no

Framing error. There may or may not be a CRC

(FCS) error.

Counters are provided to report the Receive Collision

Count and Runt Packet Count for network statistics and

utilization calculations.

Note that if the MAC engine detects a received frame

which has a 00b pattern in the preamble (after the first 8

bits which are ignored), the entire frame will be ignored.

The MAC engine will wait for the network to go inactive

before attempting to receive additional frames.

Media Access Management

The basic requirement for all stations on the network is

provide

fairness

channel

allocation.

The

802.3/Ethernet protocols define a media access mecha-

nism which permits all stations to access the channel

with equality. Any node can attempt to contend for the

channel by waiting for a predetermined time (Inter Pack-

et Gap internal) after the last activity, before transmitting

on the media. The channel is a multidrop communica-

tions media (with various topological configurations per-

mitted) which allows a single station to transmit and all

other stations to receive. If two nodes simultaneously

contend for the channel, their signals will interact caus-

ing loss of data, defined as a collision. It is the responsi-

bility of the MAC to attempt to avoid and recover from a

collision, to guarantee data integrity for the end-to-end

transmission to the receiving station.

Medium Allocation

The IEEE/ANSI 802.3 Standard (ISO/IEC 8802-3 1990)

requires that the CSMA/CD MAC monitor the medium

for traffic by watching for carrier activity. When carrier is

detected, the media is considered busy, and the MAC

should defer to the existing message.

The ISO 8802-3 (IEEE/ANSI 802.3) Standard also al-

lows optional two part deferral after a receive message.

See ANSI/IEEE Std 802.3 –1990 Edition, 4.2.3.2.1:

Note: It is possible for the PLS carrier sense indication

to fail to be asserted during a collision on the media. If

the deference process simply times the interFrame gap

based on this indication it is possible for a short inter-

Frame gap to be generated, leading to a potential recep-

tion failure of a subsequent frame. To enhance system

robustness the following optional measures, as speci-

fied

4.2.8,

are

recommended

when

Inter-

FrameSpacingPart1 is other than ZERO:

1. Upon completing a transmission, start timing the

interpacket gap, as soon as transmitting and car-

rier Sense are both false.

2. When timing an interFrame gap following recep-

tion, reset the interFrame gap timing if carrier

Sense becomes true during the first 2/3 of the in-

terFrame gap timing interval. During the final 1/3 of

the interval the timer shall not be reset to ensure

fair access to the medium. An initial period shorter

than 2/3 of the interval is permissible including

ZERO.

The MAC engine implements the optional receive two

part deferral algorithm, with a first part inter-frame-spac-

ing time of 6.0

µs. The second part of the inter-frame-

spacing interval is therefore 3.6

µs.

The PCnet-PCI controller will perform the two part de-

ferral algorithm as specified in Section 4.2.8 (Process

Deference). The Inter Packet Gap (IPG) timer will start

timing the 9.6

µs InterFrameSpacing after the receive

carrier is de-asserted. During the first part deferral (In-

terFrameSpacingPart1 – IFS1) the PCnet-PCI control-

ler will defer any pending transmit frame and respond to

the receive message. The IPG counter will be reset to

ZERO continuously until the carrier de-asserts, at which

point the IPG counter will resume the 9.6

µs count once

again. Once the IFS1 period of 6.0

µs has elapsed, the

PCnet-PCI controller will begin timing the second part

deferral (InterFrame Spacing Part 2 – IFS2) of 3.6

µs.

Once IFS1 has completed, and IFS2 has commenced,

the PCnet-PCI controller will not defer to a receive frame

if a transmit frame is pending. This means that the

PCnet-PCI controller will not attempt to receive the re-

ceive frame, since it will start to transmit, and generate a

collision at 9.6

µs. The PCnet-PCI controller will guaran-

tee to complete the preamble (64-bit) and jam (32-bit)

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