AM79C970 datasheet(118/168 Pages) AMD

118 / 168 page

P R E L I M I N A R Y

AMD

1-985

Am79C970

PREAD command will terminate

early, the PREAD bit will be

cleared to a ZERO and the

PVALID bit will remain reset with

a value of ZERO. This applies to

the

automatic

read

the

EEPROM after H_RESET as

well as to host initiated PREAD

commands. EEPROM program-

mable locations on board the

PCnet-PCI controller will be set

to their default values by such an

aborted PREAD operation. For

example, if the aborted PREAD

operation immediately followed

the H_RESET operation, then

the final state of the EEPROM

programmable locations will be

equal to the H_RESET program-

ming for those locations.

If a PREAD command is given to

the PCnet-PCI controller and the

auto-detection pin (EESK/

LED1)

indicates that no EEPROM is

present, then the EEPROM read

operation will still be attempted.

Note that at the end of the H_RE-

SET operation, a read of the

EEPROM

will

performed

automatically. This H_RESET–

generated EEPROM read func-

tion will not proceed if the

auto-detection pin (EESK/

LED1)

indicates that no EEPROM is

present.

PREAD is set to ZERO during

H_RESET and is unaffected by

S_RESET or the STOP bit.

PREAD is only writeable when

the STOP bit is set to ONE.

EEDET

EEPROM Detect. This bit indi-

cates the sampled value of the

EESK/

LED1 pin at the end of

H_RESET. This value indicates

whether or not an EEPROM is

present at the EEPROM inter-

face. If this bit is a ONE, it indi-

cates

that

EEPROM

present. If this bit is a ZERO, it in-

dicates that an EEPROM is not

present.

The value of this bit is determined

at the end of the H_RESET op-

eration. It is unaffected by S_RE-

SET or the STOP bit.

This bit is not writeable. It is read

only.

The following table indicates the

possible combinations of EEDET

and

the

existence

EEPROM and the resulting op-

erations that are possible on the

EEPROM Microwire interface:

Table 10. EEDET Combinations

EEDET Value

EEPROM

Result of Automatic EEPROM

(BCR19[3])

Connected?

Result if PREAD is Set to ONE

Read Operation Following H_RESET

EEPROM read operation is attempted.

First TWO EESK clock cycles are

Entire read sequence will occur,

generated, then EEPROM read

checksum failure will result, PVALID

operation is aborted and PVALID is

is reset to ZERO.

reset to ZERO.

Yes

EEPROM read operation is attempted.

First TWO EESK clock cycles are generated,

Entire read sequence will occur, checksum then EEPROM read operation is aborted and

operation will pass, PVALID is set to ONE.

PVALID is reset to ZERO.

EEPROM read operation is attempted.

EEPROM read operation is attempted. Entire

Entire read sequence will occur, checksum read sequence will occur, checksum failure

failure will result, PVALID is reset to ZERO. will result, PVALID is reset to ZERO.

Yes

EEPROM read operation is attempted.

Entire read sequence will occur, checksum Entire read sequence will occur, checksum

operation will pass, PVALID is set to ONE.

AM79C970 Datasheet(PDF) 118 Page - Advanced Micro Devices

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