ADA2200ARUZ datasheet(7/25 Pages) AD

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ADA2200

Data Sheet

Figure 4. Load from EEPROM Timing Diagram

Figure 5. CLKIN to RCLK, SYNCO, and OUTP/OUTN Sample Timing

Table 4. Output, SYNCO, and RCLK Timing, Default Register Settings

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

CLKIN to OUTx sample update delay

CLKIN to SYNCO delay, rising or falling edge to rising edge

SYNCO pulse width

1/fSI

CLKIN to RCLK delay, rising edge to rising or falling edge

Figure 6. Input, Output, SYNCO, and RCLK Timing Relative to CLKIN

RST

BOOT

SCL

SDA

START

b10001

R/W ACK

ACK

DATA

STOP

ADDR

[1:0]

SAMPLE 0

SAMPLE 1

SAMPLE 2

SAMPLE 3 + 4 HOLD SAMPLES

100

OUTPUT

PHASE90 = 1

CLKIN

RCLK

SYNCO

HOLD SAMPLES

SAMPLE 0

SAMPLE 1

SAMPLE 2

SAMPLE 3 + 4 HOLD SAMPLES

SAMPLE 0

SAMPLE 1

OUTPUT

PHASE90 = 0

CLKIN

RCLK

SYNCO

INx, OUTx

INN/INP

OUTN/OUTP

Rev. 0 | Page 6 of 24

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