ADA2200ARUZ datasheet(19/25 Pages) AD

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ADA2200

Data Sheet

There are several ways of digitally processing the output samples to

optimize measurement accuracy, bandwidth, and throughput

rate. One method is to take the sum of eight samples to return a

value. A moving average filter lowers the noise floor of the

returned values. The length of the moving average filter is

determined by the noise floor and settling time requirements.

INTERFACING TO MICROCONTROLLERS

The diagram in Figure 28 shows basic circuit configuration

driven by a low power microcontroller (the ADuCM361). In

this case, the ADA2200 reduces the ADC sampling rate by a

factor of 8, and reduces the subsequent signal processing

required by the microcontroller.

Figure 28. Fully Programmable Configuration:

Interface to Low Power Microcontroller

EEPROM BOOT CONFIGURATION

The diagram in Figure 29 shows a standalone configuration

with an EEPROM boot for the ADA2200. The standard

oscillator circuit between CLKIN and XOUT generates the

clock signal. Holding BOOT low during a power-on reset

(POR) forces the ADA2200 to load its configuration from a

preprogrammed EEPROM. An EEPROM boot is also initiated

by bringing the BOOT pin low while the device in not in reset.

Figure 29. Standalone Configuration

POWER DISSIPATION

The ADA2200 current draw is composed of two main

components, the amplifier bias currents and the switched

capacitor currents. The amplifier currents are independent of

clock frequency; the switched capacitor currents scale in direct

proportion to fSI.

Figure 30 shows the ADA2200 measured typical current draw at

supply voltages of 2.7 V and 3.3 V, as the input clock varies from

1 kHz to 1 MHz, with CLKIN DIV[2:0] = 1. With a 3.3 V supply

voltage, the current draw can be estimated with the following

equation:

IDD = 290 × 0.2 × fCLKIN µA

where fCLKIN is specified in kHz.

Figure 30. Typical Current Draw vs. CLKIN Frequency at VDD = 2.7 V and 3.3 V

INP

OUTP

OUTN

CLKIN

SYNCO

RST

BOOT

CS/A0

SDIO/SDA

RCLK/SDO

SCLK/SCL

AIN0

AIN1

P1.2

P0.6/IRQ2

P1.1

P1.0

P1.7/CS0

P1.6/MOSI0

P1.4/MISO0

P1.5/SCLK0

P0.3/CS1

AVDD_REG

DVDD_REG

AGND

VREF–

IOVDD

AVDD

VREF+

P0.0/MISO1

P0.2/MOSI1

P0.1/SCLK1

VOCM

XOUT

GND

VDD

ADA2200

3.3V

INN

TO HOST,

MEMORY

INTERFACE

0.47µF

×2

0.47µF

+VS

ADuCM361

NOTES

1. SOME PIN NAMES OF THE ADuCM361 HAVE BEEN SIMPLIFIED FOR CLARITY.

VDD

ADA2200

3.3V

SCL A0

SDA

SCLK/SCL

SDIO/SDA

CS/A0

EEPROM*

*AT24C02 OR EQUIVALENT

3.3V

RCLK/SDO

OUTN

OUTP

VOCM

INN

RST

BOOT

CLKIN

XOUT

INP

OUTPUT

EXCITATION

INPUT

GND

3.3V

500

250

275

300

325

350

375

400

425

450

475

1000

800

600

400

200

CLKIN FREQUENCY (kHz)

2.7V

3.3V

Rev. 0 | Page 18 of 24

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