ADA2200ARUZ datasheet(20/25 Pages) AD

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Data Sheet

ADA2200

DEVICE CONFIGURATION

The ADA2200 has several registers that can be programmed to

customize the device operation. There are two methods for

programming the registers: the device can be programmed over

the serial port interface, or the I2C master can be used to read

the configuration from a serial EEPROM.

SERIAL PORT OPERATION

The serial port is a flexible, synchronous serial communications

port that allows easy interfacing to many industry-standard micro-

controllers and microprocessors. The serial I/O is compatible

with most synchronous transfer formats, including both the

Motorola SPI and Intel® SSR protocols. The interface allows

read/write access to all registers that configure the ADA2200.

Single-byte or multiple-byte transfers are supported, as well as

MSB first or LSB first transfer formats. The serial port interface can

be configured as a single-pin I/O (SDIO) or as two unidirectional

pins for input and output (SDIO and SDO).

A communication cycle with the ADA2200 has two phases.

Phase 1 is the instruction cycle (the writing of an instruction

byte into the device), coincident with the first 16 SCLK rising

edges. The instruction byte provides the serial port controller with

information regarding the data transfer cycle—Phase 2 of the

communication cycle. The Phase 1 instruction byte defines

whether the upcoming data transfer is a read or write, along with

the starting register address for the first byte of the data transfer.

The first 16 SCLK rising edges of each communication cycle are

used to write the instruction byte into the device.

A logic high on the CS/A0 pin followed by a logic low resets the

serial port timing to the initial state of the instruction cycle.

From this state, the next 16 rising SCLK edges represent the

instruction bits of the current I/O operation.

The remaining SCLK edges are for Phase 2 of the communication

cycle. Phase 2 is the actual data transfer between the device and

the system controller. Phase 2 of the communication cycle is a

transfer of one or more data bytes. Registers change immediately

upon writing to the last bit of each transfer byte.

DATA FORMAT

The instruction byte contains the information shown in Table 9.

Table 9. Serial Port Instruction Byte

MSB

LSB

I15

I14

I13

I12

…

R/W

A14

A13

A12

…

R/W, Bit 15 of the instruction byte, determines whether a read or a

write data transfer occurs after the instruction byte write. Logic 1

indicates a read operation, and Logic 0 indicates a write operation.

A14 to A0, Bit 14 to Bit 0 of the instruction byte, determine the

communication cycle. For multibyte transfers, A14 is the starting

byte address. The remaining register addresses are generated by

the device based on the LSB first bit (Register 0x0000, Bit 6).

SERIAL PORT PIN DESCRIPTIONS

Serial Clock (SCLK/SCL)

The serial clock pin synchronizes data to and from the device

and runs the internal state machines. The maximum frequency

of SCLK is 20 MHz. All data input is registered on the rising edge

of the SCLK signal. All data is driven out on the falling edge of

the SCLK signal

Chip Select (CS/A0)

An active low input starts and gates a communication cycle.

It allows more than one device to be used on the same serial

communications lines. When the CS/A0 pin is high, the SDO

and SDIO signals go to a high impedance state. Keep the CS/A0

pin low throughout the entire communication cycle.

Serial Data I/O (SDIO/SDA)

Data is always written into the device on this pin. However, this

pin can be used as a bidirectional data line. The configuration

of this pin is controlled by Register 0x0000, Bit 3 and Bit 4. The

default is Logic 0, configuring the SDIO/SDA pin as unidirectional.

Serial Data Output (RCLK/SDO)

If the ADA2200 is configured for 4-wire SPI operation, this pin

can be used as the serial data output pin. If the device is configured

for 3-wire SPI operation, this pin can be used as an output for

the reference clock (RCLK) signal. Setting the RCLK select bit

(Register 0x002A, Bit 3) high activates the RCLK signal.

SERIAL PORT OPTIONS

The serial port can support both MSB first and LSB first data

formats. This functionality is controlled by the LSB first bit

(Register 0x0000, Bit 6). The default is MSB first (LSB first = 0).

When the LSB first bit = 0 (MSB first), the instruction and data

bits must be written from MSB to LSB. Multibyte data transfers

in MSB first format start with an instruction byte that includes the

bytes follow from high address to low address. In MSB first

mode, the serial port internal byte address generator decrements

for each data byte of the multibyte communication cycle.

When the LSB first bit = 1, the instruction and data bits must be

written from LSB to MSB. Multibyte data transfers in LSB first

format start with an instruction byte that includes the register

address of the least significant data byte. Subsequent data bytes

follow from the low address to the high address. In LSB first

mode, the serial port internal byte address generator increments

for each data byte of the multibyte communication cycle.

If the MSB first mode is active, the data address is decremented

for each successive read or write operation performed in a

multibyte register access. If the LSB first mode is active, the data

address increments for each successive read or write operation

performed in a multibyte register access.

Rev. 0 | Page 19 of 24

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