ADA2200ARUZ datasheet(11/25 Pages) AD

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ADA2200

Data Sheet

TERMINOLOGY

Cycle Mean

The cycle mean is the average of all the output samples

(OUTP/OUTN) over one RCLK period. In the default

configuration, there are eight output samples per RCLK cycle;

thus, the cycle mean is the average of eight consecutive output

samples. If the device is reconfigured such that the frequency of

RCLK is fSO/4, then the cycle mean is the average of four

consecutive output samples.

Conversion Gain

Conversion gain is calculated as follows:

Gain

Conversion

where:

I is the offset corrected cycle mean, PHASE90 bit = 0.

Q is the offset corrected cycle mean, PHASE90 bit = 1.

VIN is the rms value of the input voltage.

The offset corrected cycle mean = cycle mean − output offset.

Relative Phase (θREL)

Relative phase is the phase difference between the rising

positive zero crossing of a sine wave at the INN/INP inputs

relative to the next rising edge of RCLK.

Figure 14. Example Showing Relative Phase, θREL, of 37°

Phase Delay (°θDELAY)

The phase delay is the relative phase (θREL) that produces a zero

cycle mean output value for a sine wave input with a frequency

equal to fRCLK. The phase delay is the relative phase value that

corresponds to the positive zero crossing of the phase measurement

transfer function.

Phase Measurement Transfer Function

Figure 15 shows the cycle mean value of the output for a

1 V rms input sine wave as θREL is swept from 0° to 360°.

Figure 15. Phase Transfer Function with Phase Delay of 83°, 1 V rms Input

100

150

200

250

300

350

RCLK

INP/INN

PHASE (Degrees)

RELATIVE

PHASE = 37°

1.2

–1.2

–1.0

–0.8

–0.6

–0.4

–0.2

0.2

0.4

0.6

0.8

1.0

83°

135

180

225

270

315

360

RELATIVE PHASE (

θREL)

Rev. 0 | Page 10 of 24

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