Data Sheet

ADA2200

Name

Address

(Hex)

Bits

Bit Name

Description

Default1

Clock

Configuration

0x002B

[4:2]

CLKIN DIV[2:0]

000

000 = divide by 1.

001 = divide by 16.

010 = divide by 64.

100 = divide by 256.

[1:0]

RCLK DIV[1:0]

10

00 = reserved.

11 = reserved.

Digital Pin

Configuration

0x002C

0

RCLK/SDO output

enable

1 = RCLK/SDO output pad driver is enabled.

1

Core Reset

0x002D

0

Core reset

1 = puts the device core into reset. The values of the SPI registers

are preserved. This does not initiate a boot from the EEPROM.

0

0 = core reset is deasserted.

Checksum

0x002E

[7:0]

Checksum value[7:0]

This is the 8-bit checksum calculated by the ADA2200, performed

on the data it reads from the EEPROM.

N/A

EEPROM

Status

0x002F

2

Checksum failed

1 = calculated checksum does not match the checksum byte read

from the EEPROM.

N/A

1

Checksum passed

1 = calculated checksum matches the checksum byte read from

the EEPROM.

N/A

0

Boot from EEPROM

complete

1 = boot from the EEPROM has completed.

N/A

0 = boot from the EEPROM has timed out. Wait 10,000 clock

cycles after the boot is initiated to check for boot completion.

1

NA/ means not applicable.

2

The filter coefficients listed are the default values programmed into the filter on reset. The value read back from the registers is 0x00.

Figure 33. Detailed Block Diagram

1

0

1

0

INP

INN

CLKIN

XOUT

VOCM

RCLK/SDO

OUTN

OUTP

VDD

LPF

8

÷8

SYNCO

SCLK/SCL

SDIO/SDA

CS/A0

CONTROL

REGISTERS

MASTER

RST

BOOT

ADA2200

0x0028[1]

0x0024

TO

0x0027

0x002A[4]

0x002A[6]

{000,001,010,100}

÷ {1,16,64,256}

0x002B[4:2]

{1,0}

÷ {4,8}

0x002B[0]

BPF

S/H

VOCM

GEN

0x002A[2:0]

0x002A[3]

0x002C[0]

0x0029[3:0]

0x0029[5]

0x0029[4]

0x0028[0]

90°

0

1

0

1

EN

RCLK

TRI

SYNC

GEN

EN

EN

÷32

CLKIN

SDO

Rev. 0 | Page 23 of 24