ADA2200ARUZ datasheet(14/25 Pages) AD

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Data Sheet

ADA2200

IIR FILTER

The IIR block operates at the output sample rate, fSO, which is at

1/8th of the input sample rate (fSI). By default, the IIR filter is

configured as a band-pass filter with a center frequency at fSO/8

(fSI/64). This frequency corresponds to the default mixing

frequency and assures that input signals in the center of the pass

band mix down to dc.

Figure 22 shows the default frequency response of the IIR filter.

Figure 22. Default IIR Filter Frequency Response (fSO/8 BPF)

If a different frequency response is required, the IIR can be

programmed for a different response. Register 0x0011 through

filter response. To program the filter, first load the configuration

registers (Register 0x0011 through Register 0x0027) with the

desired coefficients. The coefficients can then be loaded into the

filter by writing 0x03 to Register 0x0010.

The IIR filter can be configured for all pass operation by

loading the coefficients listed in Table 8.

Table 8. IIR Coefficients for the All Pass Filter

Value

0x0011

0xC0

0x0012

0x0F

0x0013

0x1D

0x0014

0xD7

0x0015

0xC0

0x0016

0x0F

0x0017

0xC0

0x0018

0x0F

0x0019

0x1D

0x001A

0x97

0x001B

0x7E

0x001C

0x88

0x001D

0xC0

0x001E

0x0F

0x001F

0xC0

0x0020

0x0F

0x0021

0xC0

0x0022

0x0F

0x0023

0x00

0x0024

0x0E

0x0025

0x23

0x0026

0x02

0x0027

0x24

MIXER

The ADA2200 performs the mixing function by holding the

output samples constant for ½ of the RCLK period. This is

similar to a half-wave rectification function except that the

output does not return to zero for ½ the output period, but

retains the value of the previous sample.

In the default configuration, there are eight output sample periods

during each RCLK cycle. There are four updated output samples

while the RCLK signal is high. While RCLK is low, the fourth

updated sample is held constant for four additional output

sample periods. The timing of the output samples in the default

configuration is shown in Table 4.

The RCLK divider, RCLK DIV[1:0], can be set to divide fSO by 4.

When this mode is selected, four output sample periods occur

during each RCLK cycle. Two output samples occur while the

RCLK signal is high. While RCLK is low, the second updated

sample is held constant for two additional output sample periods.

The mixer can be bypassed. When the mixer is bypassed, the output

produces an updated sample value every output sample period.

NORMALIZED FREQUENCY (Hz/Nyquist)

–10

–40

–50

0.50

0.75

1.00

–20

–30

0.25

Rev. 0 | Page 13 of 24

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