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ADA2200

Data Sheet

Phase Shifter

It is possible to change the timing of the output samples with

respect to RCLK by writing to the PHASE90 bit in Register

0x002A. When the alternative timing option is selected, two

output samples are updated while RCLK is low, and two are

updated while RCLK is high. The second sample, which is taken

while RCLK is high, is held four additional output sample

periods. The timing is shown in Figure 5.

Applying a 90° phase shift can be useful in a number of instances. It

enables a pair of ADA2200 devices to perform in phase and

quadrature demodulation. A 90° phase shift can also be useful in

control systems for selecting an appropriate error signal output.

Figure 23. Output Sample Timing Relative to RCLK,

(A) PHASE90 = 0, (B) PHASE90 = 1

CLOCKING OPTIONS

The ADA2200 has several clocking options to make system

integration easier.

Clock Dividers

The ADA2200 has a pair of on-chip clock dividers to generate

the system clocks. The input clock divider, CLKIN DIV[2:0], sets

the input sample rate of the decimator (fSI) by dividing the CLKIN

signal. The value of CLKIN DIV[2:0] can be set to 1, 16, 64, or 256.

The output sample rate (fSO) is always 1/8th of the decimator

input sample rate.

The RCLK divider, RCLK DIV[1:0], sets the frequency of the

mixer frequency, fM (which is also the frequency of RCLK) by

dividing fSO by either 4 or 8.

Synchronization Pulse Output

The ADA2200 generates an output pulse (SYNCO), which can

be used by a microprocessor or directly by an ADC to initiate

an analog to digital conversion of the ADA2200 output. The

SYNCO signal ensures that the ADC sampling occurs at an

optimal time during the ADA2200 output sample window.

One output sample of the ADA2200 is 8 fSI clock cycles long.

The SYNCO pulse is 1 fSI clock cycle in duration. As shown in

Figure 24, the SYNCO pulse can be programmed to occur at 1

of 16 different timing offsets. The timing offsets are spaced at ½

fSI clock cycle intervals and span the full output sample window.

The SYNCO pulse can be inverted, or the SYNCO output can

be disabled. The operation of the SYNCO timing generation

configuration settings are contained in Register 0x0029.

Figure 24. SYNCO Output Timing Relative to OUTP/OUTN, INP/INN,

and CLKIN

(A)

(B)

INx, OUTx

SYNCO (0)

SYNCO (1)

SYNCO (13)

SYNCO (14)

SYNCO (15)

CLKIN

Rev. 0 | Page 14 of 24

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