ADA2200ARUZ datasheet(21/25 Pages) AD

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ADA2200

Data Sheet

Figure 31. Serial Port Interface Timing, MSB First

Figure 32. Serial Port Interface Timing, LSB First

BOOTING FROM EEPROM

The device can load the internal registers from the EEPROM using

the internal I2C master to customize the operation of the ADA2200.

To enable this feature, the user must control either the RST pin

or the BOOT pin. In either case, the device boots from the

EEPROM only when it is out of reset and the master clock is active.

Enabling Load from Memory

A boot from the EEPROM is initiated by two methods.

To initiate loading via the BOOT pin, the device must be out of

reset, and the BOOT pin is brought low for a minimum of two

clock cycles of the master clock. After it is initiated, the boot

completes irrespective of the state of the BOOT pin. To initiate

subsequent boots, the BOOT pin must be brought high and

then low for a minimum of two clock cycles of the master clock.

To initiate loading via the RST pin, the BOOT pin must be low.

The RST pin can be tied high and the ADA2200 loads from the

EEPROM when the device is powered up and the internal POR

cycle completes. To initiate subsequent boots, the ADA2200 can

be power cycled or the RST pin can be brought low and then high.

The SPI interface is disabled while the ADA2200 is loading the

EEPROM.

Load from Memory Cycle

The ADA2200 reads the first 28 bytes of the EEPROM. The first

27 bytes represent the contents to be loaded into Register 0x0011 to

EEPROM.

The ADA2200 calculates the checksum for the first 27 bytes that

it reads back and compares it to the checksum in the EEPROM.

The ADA2200 calculated checksum is accessible by reading the

EEPROM checksum register (Register 0x002E). If the ADA2200

checksum matches the checksum stored in the EEPROM, the

load from the EEPROM was successful. The load from the

EEPROM pass or fail status is recorded in the EEPROM status

In addition, the LSB of the EEPROM status register indicates

whether the load cycle is complete. Logic 1 represents successful

completion of the load cycle. Logic 0 represents the occurrence of

a timeout violation during the loading cycle. In the event of a time-

out or the successful completion of the load from a memory cycle,

the ADA2200 I2C master interface disables, and the ADA2200

SPI interface reenables, allowing the user communication access to

the device.

The load cycle completes within 10,000 clock cycles of CLKIN

(or CLKIN divided by the current value of CLKIN DIV[2:0] if

the load cycle is being initiated by the BOOT pin).

Dual Configuration/Dual Device Memory Load

The CS/A0 pin allows a single EEPROM device to support a dual

configuration for a single ADA2200 device or different

configurations for two different ADA2200 devices. To ensure

reliable operation, set the CS/A0 pin to the desired state before

initiating a boot, and then hold the state for the entire duration

of the boot.

To configure a single ADA2200 device, the EEPROM must have a

word page size that supports a minimum of 32 words, each of 8 bits

per word. To support two devices, or a dual configuration for a

single device, the EEPROM must have at least two word pages.

The ADA2200 configuration data for each device must be

allocated to the EEPROM memory within a single word page.

Using SPI Master with EEPROM Loading

The load from a memory cycle requires an I2C communication

bus between the ADA2200 and the EEPROM device; however,

the ADA2200 can still be controlled by the SPI interface after the

load from the memory cycle is complete. It is recommended that

the CS/A0 pin return to logic high after the load from the memory

cycle and before the first SPI read or write command. This allows

the user to ensure that the proper setup time elapses before the

initiation of a SPI read/write command (see Table 2).

R/W A14 A13

A0 D7N D6N D5N

D00

D10

D20

D30

INSTRUCTION CYCLE

DATA TRANSFER CYCLE

SCLK

SDIO

A12 A13 A14

D00 D10 D20

D7N

D6N

D5N

D4N

INSTRUCTION CYCLE

DATA TRANSFER CYCLE

SCLK

SDIO

R/W

Rev. 0 | Page 20 of 24

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