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ADA2200ARUZ Datasheet(PDF) 23 Page - Analog Devices |
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ADA2200ARUZ Datasheet(HTML) 23 Page - Analog Devices |
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23 / 25 page  ADA2200 Data Sheet Name Address (Hex) Bits Bit Name Description Default1 Filter Strobe 0x0010 [7:0] Load coefficients[1:0] When toggled from 0 to 1, the filter coefficients in configuration Register 0x0011 through Register 0x0027 are loaded into the IIR filter. 00 Filter Configuration 0x0011 [7:0] Coefficient[7:0] Programmable filter coefficients. 0xC022 0x0012 [7:0] Coefficient[7:0] Programmable filter coefficients. 0x0F2 0x0013 [7:0] Coefficient[7:0] Programmable filter coefficients. 0x1D2 0x0014 [7:0] Coefficient[7:0] Programmable filter coefficients. 0xD72 0x0015 [7:0] Coefficient[7:0] Programmable filter coefficients. 0xC02 0x0016 [7:0] Coefficient[7:0] Programmable filter coefficients. 0x0F2 0x0017 [7:0] Coefficient[7:0] Programmable filter coefficients. 0xC02 0x0018 [7:0] Coefficient[7:0] Programmable filter coefficients. 0x0F2 0x0019 [7:0] Coefficient[7:0] Programmable filter coefficients. 0x1D2 0x001A [7:0] Coefficient[7:0] Programmable filter coefficients. 0x972 0x001B [7:0] Coefficient[7:0] Programmable filter coefficients. 0x7E2 0x001C [7:0] Coefficient[7:0] Programmable filter coefficients. 0x882 0x001D [7:0] Coefficient[7:0] Programmable filter coefficients. 0xC02 0x001E [7:0] Coefficient[7:0] Programmable filter coefficients. 0x0F2 0x001F [7:0] Coefficient[7:0] Programmable filter coefficients. 0xC02 0x0020 [7:0] Coefficient[7:0] Programmable filter coefficients. 0x0F2 0x0021 [7:0] Coefficient[7:0] Programmable filter coefficients. 0xC02 0x0022 [7:0] Coefficient[7:0] Programmable filter coefficients. 0x0F2 0x0023 [7:0] Coefficient[7:0] Programmable filter coefficients. 0x002 0x0024 [7:0] Coefficient[7:0] Programmable filter coefficients. 0xE02 0x0025 [7:0] Coefficient[7:0] Programmable filter coefficients. 0x232 0x0026 [7:0] Coefficient[7:0] Programmable filter coefficients. 0x022 0x0027 [7:0] Coefficient[7:0] Programmable filter coefficients. 0x242 Analog Pin Configuration 0x0028 1 INP gain 1 = only the INP input signal is sampled. An additional 6 dB of gain is applied to the signal path. 0 0 Clock source select 0 = device is configured to generate a clock if a crystal or resonator is placed between the XOUT and CLKIN pins. 0 1 = device is configured to accept a CMOS level clock on the CLKIN pin. The internal XOUT driver is disabled. Sync Control 0x0029 5 SYNCO output enable 1 = enables the SYNCO output pad driver. 1 4 SYNCO invert 1 = inverts the SYNCO signal. 0 [3:0] SYNCO edge select These bits select one of 16 different edge locations for the SYNCO pulse relative to the output sample window. See Figure 24 for details. 1101 Demod Control 0x002A 6 PHASE90 1 = delays the phase between the RCLK output and the strobe controlling the mixing signal. See Figure 23 for details. 0 4 Mixer enable 1 = the last sample that is taken while RCLK is active remains held while RCLK is inactive. 1 3 RCLK select 0 = sends the SDO signal to the output driver of Pin 13. 1 1 = sends the RCLK signal to the output driver of Pin 13. [2:0] VOCM select 000 = set the VOCM pin to VDD/2. Low power mode. 000 001 = use the external reference to drive VOCM. 010 = set the VOCM pin to VDD/2. Fast settling mode. 101 = set the VOCM pin to 1.2 V. Rev. 0 | Page 22 of 24 |
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