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ZSC31014 Datasheet(PDF) 28 Page - Integrated Device Technology |
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ZSC31014 Datasheet(HTML) 28 Page - Integrated Device Technology |
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28 / 58 page ![]() ZSC31014 Datasheet © 2016 Integrated Device Technology, Inc. 28 January 20, 2016 3.1.1. Update Mode In Update Mode, the digital core will perform measurements and correction calculations at a selectable update rate and update the I 2C™/SPI output register. The power-on measurement sequence for the Update Mode is shown in Figure 3.2. Figure 3.2 Power-Up Sequence and Timing for Update Mode with EEPROM Locked § If the part is programmed for the fastest update rate, conversions will continue to happen after the power-up sequence. If the ZSC31014 is not in the fastest update rate, the part will power down after writing to the digital output register. The duration of the power-down period is determined by the Update_Rate setting (bits [7:6] in EEPROM word 01HEX; see section 3.6) and the digital core clock speed (see section 2.3.6). See Table 3.2 and Table 3.3 for the update rates. After the power-down period has expired, the ZSC31014 will power up; take another bridge reading followed by calculations; write to the digital output register; and power down. Temperature and Auto-Zero (AZ) are slower moving quantities but must be updated periodically. When the part is configured in Update Mode, these two quantities are measured periodically (referred to as special measurements). As illustrated in Figure 3.3, valid data output to the digital register occurs after the measurement and the DSP calculations are complete. At this point the master can fetch the data in I 2C™ or SPI with a Read_DF command. Specifics of the Read_DF command are given in sections 3.2 and 3.3. After a valid output has been read by the master, the status bits are set to “stale,” indicating that the measurement has not been updated since the last Read_DF. This mode allows the application to simply read the digital output at any time and be assured the data is no older than the selected update period. See Table 2.9 for more information on the status bits. The chip should be polled at a frequency slower than 20% more of the update rate period listed in Table 3.2 and Table 3.3. In I 2C™ Mode only, the INT/SS pin will assume the INT (interrupt) function. Instead of polling until a “valid” response is received, the application can look for a rise on the INT pin. This will indicate that the measurement and calculations are complete and new valid data is ready to be read on the I 2C™ interface. § When EEPROM is not locked, the command window is 4.5ms longer (= 6ms). All time values shown are typical; for the worst case values, multiply by 1.15 (nominal frequency ±15%). Command Window Temperature Measurement AutoZero (AZ) Measurement Bridge Measurement 1.5ms 1.4ms 400 µs Power applied to device. Command window starts after a short power-on-reset window. DSP Calculations 1 st corrected signal measurement written to digital output register (I 2C™ or SPI) 1.4ms 400 µs 1.4ms 400 µs 220 µs 60 µs With 1MHz CLK execution time With 4MHz CLK execution time |
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