DS2196 datasheet(66/157 Pages) DALLAS

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DS2196

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Table 8-1: LINE CODE VIOLATION COUNTING ARRANGEMENTS

COUNT EXCESSIVE

ZEROS

(RCR1.7)

B8ZS ENABLED

(CCR2.2)

WHAT IS COUNTED

IN THE LCVCRs

BPVs

yes

BPVs + 16 consecutive

zeros

yes

BPVs (B8ZS code words

not counted)

yes

BPV’s + 8 consecutive

zeros

Path Code Violation Count Register (PCVCR) When the receive side of a framer is set to operate in the

ESF framing mode (CCR2.3=1), PCVCR will automatically be set as a 12–bit counter that will record

errors in the CRC6 code words. When set to operate in the D4 framing mode (CCR2.3=0), PCVCR will

automatically count errors in the Ft framing bit position. Via the RCR2.1 bit, a framer can be

programmed to also report errors in the Fs framing bit position. The PCVCR will be disabled during

receive loss of synchronization (RLOS=1) conditions. See Table 8-2 for a detailed description of exactly

what errors the PCVCR counts.

PCVCR1A: PATH VIOLATION COUNT REGISTER 1 FRAMER A (Address = 25 Hex)

PCVCR2A: PATH VIOLATION COUNT REGISTER 2 FRAMER A (Address = 26 Hex)

PCVCR1B: PATH VIOLATION COUNT REGISTER 1 FRAMER B (Address = C5 Hex)

PCVCR2B: PATH VIOLATION COUNT REGISTER 2 FRAMER B (Address = C6 Hex)

(MSB)

(LSB)

(note 1)

CRC/

FB11

CRC/

FB10

CRC/

FB9

CRC/

FB8

PCVCR1

CRC/

FB7

CRC/

FB6

CRC/

FB5

CRC/

FB4

CRC/

FB3

CRC/

FB2

CRC/

FB1

CRC/

FB0

PCVCR2

SYMBOL

POSITION

NAME AND DESCRIPTION

CRC/FB11

PCVCR1.3

MSB of the 12–Bit CRC6 Error or Frame Bit Error Count

(note #2)

CRC/FB0

PCVCR2.0

LSB of the 12–Bit CRC6 Error or Frame Bit Error Count

(note #2)

NOTES:

1. The upper nibble of the counter at address 25 is used by the Multiframes Out of Sync Count Register

2. PCVCR counts either errors in CRC code words (in the ESF framing mode; CCR2.3=1) or errors in

the framing bit position (in the D4 framing mode; CCR2.3=0).

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