DS2196 datasheet(18/157 Pages) DALLAS

18 / 157 page

DS2196

18 of 157

Signal Type:

Output

This digital output will provide either a frame synchronization pulse or the negative half of a bipolar data stream.

The signal is based on what is provided at the TNEGLI input.

Signal Name:

LNRZ

Signal Description:

LIU NRZ Data

Signal Type:

Output

This digital output will provide either a NRZ data stream or the positive half of a bipolar data stream. The signal is

based on what is provided at the TPOSLI input.

Signal Name:

LCLK

Signal Description:

LIU Clock

Signal Type:

Output

This digital output provides the 1.544 MHz transmit LIU clock. The signal is based on what is provided at the

TCLKLI input.

Signal Name:

TNEGLI

Signal Description:

Transmit Negative Data for the LIU

Signal Type:

Input

This digital input is used to pass either the negative half of a bipolar data stream or a frame synchronization pulse

via the jitter attenuator block to the transmit line driver block and the LFSYNC output pin. Data input to this pin is

sampled on the falling edge of TCLKLI. TNEGLI can be internally connected to TNEGOA/TFSYNCA via the

CCR4A.2 control bit.

Signal Name:

TPOSLI

Signal Description:

Transmit Positive Data for the LIU

Signal Type:

Input

This digital input is used to pass either the positive half of a bipolar data stream or a NRZ data stream via the jitter

attenuator block to the transmit line driver block and the LNRZ output pin. Data input to this pin is sampled on the

falling edge of TCLKLI. TPOSLI can be internally connected to TPOSOA/TNRZA via the CCR4A.2 control bit.

Signal Name:

TCLKLI

Signal Description:

Transmit Clock for the LIU

Signal Type:

Input

This digital input is used to pass a 1.544 MHz clock via the jitter attenuator block to the transmit line driver block

and the LCLK output pin. TCLKLI can be internally connected to TCLKOA via the CCR4A.2 control bit.

Signal Name:

WNRZ

Signal Description:

Working NRZ Data

Signal Type:

Input

This digital input is used to pass a NRZ data stream via the Data Source Selection MUX and the jitter attenuator

block to the RPOSLO and RNEGLO output pins. Data input to this pin is sampled on the falling or rising edge of

WCLK.

Signal Name:

WCLK

Signal Description:

Working Clock

Signal Type:

Input

This digital input is used to pass a 1.544 MHz clock via the Data Source Selection MUX and the jitter attenuator

block to the RCLKLO output pin.

DS2196 Datasheet(PDF) 18 Page - Dallas Semiconductor

DS2196 Datasheet(HTML) 18 Page - Dallas Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL