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DAC38RF86 Datasheet(PDF) 53 Page - Texas Instruments

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Part # DAC38RF86
Description  Dual- or Single-Channel, Single-Ended, 14-bit, 9-GSPS, RF-Sampling DAC with JESD204B Interface and On-Chip GSM PLL
PDF  141 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

DAC38RF86 Datasheet(HTML) 53 Page - Texas Instruments

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DAC38RF86, DAC38RF87
DAC38RF97, DAC38RF96
www.ti.com
SLASEF4 – FEBRUARY 2017
Product Folder Links: DAC38RF86 DAC38RF87 DAC38RF97 DAC38RF96
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
The PAP block keeps track of the input signal power by maintaining a sliding window accumulation of last N
samples. N is selectable to be 32, 64 or 128 based on the setting (Table 38) of fields PAPAB_SEL_DLY in
register PAP_CFG_AB (8.5.35) and PAPCD_SEL_DLY in register PAP_CFG_CD (8.5.36). The average
amplitude of input signal is computed by dividing accumulated value by the number of samples in the delay-line
(N). The result is then compared against the threshold in fields PAPAB_THRESH in register PAP_CFG_AB
(8.5.35) and PAPCD_THRESH in register PAP_CFG_CD (8.5.36). If the threshold is violated, gain state machine
is triggered which generated gain value to ramp down the DAC output signal amplitude. After the input signal
returns to normal value, the state machine ramps up the DAC output signal amplitude.
Table 38. PAP Delay Line Selection
pap_sel_dly[1:0]
# of samples averaged
00
32
01
64
10
128
11
Reserved
The generation of the PAP trigger as explained as follows:
•
The I and Q samples are treated separately – either can trigger attenuation
•
In dual DUC modes, each IQ pair is treated separately and has a separate gain block
•
8 samples at the input are put through an absolute value circuit (all 2’s complement)
•
Next these values are vector summed to get a 12 bit result
•
Then 12 bit result is placed into the delay line and summed into the accumulator
•
The accumulator is also subtracting out the delayed 12 bit word corresponding to N = 32, N = 64 or N = 128
•
Finally the accumulator output is divided down by N and rounded to 13 bits. These 13 bits are compared to
the threshold in the SPI registers. A pap_trig occurs if the threshold is exceeded.
The PAP gain state machine generates the pap gain value to be applied on the output stream to reduce the
output signal amplitude. The state machine below is used to control the attenuation of the DAC output and the
gaining up of the signal again once the trigger is released.
Figure 43. PAP Gain State Machine
The normal operating condition for the PAP block is the NORMAL state in Figure 43. However, when the PAP
block detects an error condition it sets the pap_trig signal to ‘1’ causing a state transition from NORMAL
operation to the ATTENUATE state.



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