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DAC38RF86 Datasheet(PDF) 85 Page - Texas Instruments |
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DAC38RF86 Datasheet(HTML) 85 Page - Texas Instruments |
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85 / 141 page ![]() 85 DAC38RF86, DAC38RF87 DAC38RF97, DAC38RF96 www.ti.com SLASEF4 – FEBRUARY 2017 Product Folder Links: DAC38RF86 DAC38RF87 DAC38RF97 DAC38RF96 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated 8.5.29 Sync Source Control 1 Register (address = 0x27) [reset = 0x1144] Figure 80. Sync Source Control 1 Register (SYNCSEL1) 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 x R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 0 0 1 0 0 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 70. SYNCSEL1 Field Descriptions Bit Field Type Reset Description 15:12 SYNCSEL_MIXERAB R/W 0x1 Controls the syncing of the double buffered SPI registers for the mixerAB block. These bits are enables so a ‘1’ in the bit place allows the sync to pass to the block. bit 0 = auto-sync from SPI register write bit 1 = sysref bit 2 = sync_out from JESD bit 3 = mem_spi_sync 11:8 SYNCSEL_MIXERCD R/W 0x1 Controls the syncing of the double buffered SPI registers for the mixerCD block. These bits are enables so a ‘1’ in the bit place allows the sync to pass to the block. bit 0 = auto-sync from SPI register write bit 1 = sysref bit 2 = sync_out from JESD bit 3 = mem_spi_sync 7:4 SYNCSEL_NCOAB R/W 0x4 Controls the syncing of NCOAB accumulators. These bits are enables so a ‘1’ in the bit place allows the sync to pass to the block. bit 0 = ‘0’ bit 1 = sysref bit 2 = sync_out from JESD bit 3 = mem_spi_sync 3:0 SYNCSEL_NCOCD R/W 0x4 Controls the syncing of NCOCD accumulators. These bits are enables so a ‘1’ in the bit place allows the sync to pass to the block. bit 0 = ‘0’ bit 1 = sysref bit 2 = sync_out from JESD bit 3 = mem_spi_sync |
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