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DAC38RF86 Datasheet(PDF) 64 Page - Texas Instruments |
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DAC38RF86 Datasheet(HTML) 64 Page - Texas Instruments |
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64 / 141 page  64 DAC38RF86, DAC38RF87 DAC38RF97, DAC38RF96 SLASEF4 – FEBRUARY 2017 www.ti.com Product Folder Links: DAC38RF86 DAC38RF87 DAC38RF97 DAC38RF96 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Register Maps (continued) Table 41. Register Summary (continued) Address Reset Acronym Register Name Section 0x4C 0x1303 JESD_K_L JESD K and L Parameters 8.5.47 0x4D 0x0100 JESD_M_S JESD M and S Parameters 8.5.48 0x4E 0x0F4F JESD_N_HD_SCR JESD N, HD and SCR Parameters 8.5.49 0x4F 0x1CC1 JESD_MATCH JESD Character Match and Other 8.5.50 0x50 0x0000 JESD_LINK_CFG JESD Link Configuration Data 8.5.51 0x51 0x00FF JESD_SYNC_REQ JESD Sync Request 8.5.52 0x52 0x00FF JESD_ERR_OUT JESD Error Output 8.5.53 0x53 0x0100 JESD_ILA_CFG1 JESD Configuration Value used for ILA Check 8.5.54 0x54 0x8E60 JESD_ILA_CFG2 JESD Configuration Value used for ILA Check 8.5.55 0x55-0x5B 0x0000 Reserved Reserved 0x5C 0x0001 JESD_SYSR_MODE JESD SYSREF Mode 8.5.56 0x5D-0x5E 0x0000 Reserved Reserved 0x5F 0x0123 JESD_CROSSBAR1 JESD Crossbar Configuration 1 8.5.57 0x60 0x4567 JESD_CROSSBAR2 JESD Crossbar Configuration 2 8.5.58 0x61-0x63 0x0000 Reserved Reserved 0x64 0x0000 JESD_ALM_L0 JESD Alarms for Lane 0 8.5.59 0x65 0x0000 JESD_ ALM_L1 JESD Alarms for Lane 1 8.5.60 0x66 0x0000 JESD_ ALM_L2 JESD Alarms for Lane 2 8.5.61 0x67 0x0000 JESD_ALM_L3 JESD Alarms for Lane 3 8.5.62 0x68 0x0000 JESD_ALM_L4 JESD Alarms for Lane 4 8.5.63 0x69 0x0000 JESD_ALM_L5 JESD Alarms for Lane 5 8.5.64 0x6A 0x0000 JESD_ALM_L6 JESD Alarms for Lane 6 8.5.65 0x6B 0x0000 JESD_ALM_L7 JESD Alarms for Lane 7 8.5.66 0x6C 0x0000 ALM_SYSREF_PAP SYSREF and PAP Alarms 8.5.67 0x6D 0x0000 ALM_CLKDIV1 Clock Divider Alarms 1 8.5.68 0x6E-0x77 0x0000 Reserved Reserved Miscellaneous Configuration Registers (PAGE_SET[1:0] = 00, PAGE_SET[2] = 1) 0x0A 0xFC03 CLK_CONFIG Clock Configuration 8.5.69 0x0B 0x0022 SLEEP_CONFIG Sleep Configuration 8.5.70 0x0C 0xA002 CLK_OUT Divided Output Clock Configuration 8.5.71 0x0D 0xF000 DACFS DAC Fullscale Current 8.5.72 0x0E-0x0F 0x0000 Reserved Reserved 0x10 0x0000 LCMGEN Internal sysref generator 8.5.73 0x11 0x0000 LCMGEN_DIV Counter for internal sysref generator 8.5.74 0x12 0x0000 LCMGEN_SPISYSREF SPI SYSREF for internal sysref generator 8.5.75 0x13-0x1A 0x0000 Reserved Reserved 0x1B 0x0000 DTEST Digital Test Signals 8.5.76 0x1C-0x22 0x0000 Reserved Reserved 0x23 0x03F3 SLEEP_CNTL Sleep Pin Control 8.5.77 0x24 0x1000 SYSR_CAPTURE SYSREF Capture Circuit Control 8.5.78 0x25-0x30 0x0000 Reserved Reserved 0x31 0x0200 CLK_PLL_CFG Clock Input and PLL Configuration 8.5.79 0x32 0x0308 PLL_CONFIG1 PLL Configuration 1 8.5.80 0x33 0x4018 PLL_CONFIG2 PLL Configuration 2 8.5.81 0x34 0x0000 LVDS_CONFIG LVDS Output Configuration 8.5.82 0x35 0x0018 PLL_FDIV Fuse farm clock divider 8.5.83 0x36-0x3A 0x0000 Reserved Reserved 0x3B 0x0002 SRDS_CLK_CFG Serdes Clock Configuration 8.5.84 |
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