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DAC38RF86 Datasheet(PDF) 63 Page - Texas Instruments |
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DAC38RF86 Datasheet(HTML) 63 Page - Texas Instruments |
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63 / 141 page  63 DAC38RF86, DAC38RF87 DAC38RF97, DAC38RF96 www.ti.com SLASEF4 – FEBRUARY 2017 Product Folder Links: DAC38RF86 DAC38RF87 DAC38RF97 DAC38RF96 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Register Maps (continued) Table 41. Register Summary (continued) Address Reset Acronym Register Name Section 0x0A-0x77 0x0000 Reserved Reserved 0x78 0x0000 SYSREF_ALIGN_R SYSERF Align to r1 and r3 Count 8.5.9 0x79 0x0000 SYSREF12_CNT SYSREF Phase Count 1 and 2 8.5.10 0x7A 0x0000 SYSREF34_CNT SYSREF Phase Count 3 and 4 8.5.11 0x7B-0x7E 0x0000 Reserved Reserved 0x7F 0x0008 VENDOR_VER Vendor ID and Chip Version 8.5.12 Multi-DUC Configuration Registers (PAGE_SET[0] = 1 for multi-DUC1, PAGE_SET[1] = 1 for multi-DUC2) 0x0A 0x02B0 MULTIDUC_CFG1 Multi-DUC Configuration (PAP, Interpolation) 8.5.13 0x0B 0x0000 Reserved Reserved 0x0C 0x2402 MULTIDUC_CFG2 Multi-DUC Configuration (Mixers) 8.5.14 0x0D 0x8300 JESD_FIFO JESD FIFO Control 8.5.15 0x0E 0x00FF ALM_MASK1 Alarm Mask 1 8.5.16 0x0F 0x1F83 ALM_MASK2 Alarm Mask 2 8.5.17 0x10 0xFFFF ALM_MASK3 Alarm Mask 3 8.5.18 0x11 0xFFFF ALM_MASK4 Alarm Mask 4 8.5.19 0x12 0x0000 JESD_LN_SKEW JESD Lane Skew 8.5.20 0x13-0x16 0x0000 Reserved Reserved 0x17 0x0000 CMIX CMIX Configuration 8.5.21 0x18 0x0000 Reserved Reserved 0x19 0x0000 OUTSUM Output Summation and Delay 8.5.22 0x1A-0x1B 0x0000 Reserved Reserved 0x1C 0x0000 PHASE_NCOAB Phase offset for AB path NCO 8.5.23 0x1D 0x0000 PHASE_NCOCD Phase offset for CD path NCO 8.5.24 0x1E-0x20 0x0000 FREQ_NCOAB Frequency for AB path NCO 8.5.25 0x21-0x23 0x0000 FREQ_NCOCD Frequency for CD path NCO 8.5.26 0x24 0x0010 SYSREF_CLKDIV SYSREF Use for Clock Divider 8.5.27 0x25 0x7700 SERDES_CLK Serdes Clock Control 8.5.28 0x26 0x0000 Reserved Reserved 0x27 0x1144 SYNCSEL1 Sync Source Selection 8.5.29 0x28 0x0000 SYNCSEL2 Sync Source Selection 8.5.30 0x29 0x0000 PAP_GAIN_AB PAP path AB Gain Attenuation Step 8.5.31 0x2A 0x0000 PAP_WAIT_AB PAP path AB Wait Time at Gain = 0 8.5.32 0x2B 0x0000 PAP_GAIN_CD PAP path CD Gain Attenuation Step 8.5.33 0x2C 0x0000 PAP_WAIT_CD PAP path CD Wait Time at Gain = 0 8.5.34 0x2D 0x1FFF PAP_CFG_AB PAP path AB Configuration 8.5.35 0x2E 0x1FFF PAP_CFG_CD PAP path CD Configuration 8.5.36 0x2F 0x0000 SPIDAC_TEST1 Configuration for DAC SPI Constant 8.5.37 0x30 0x0000 SPIDAC_TEST2 DAC SPI Constant 8.5.38 0x31 0x0000 Reserved Reserved 0x32 0x0800 GAINAB Gain for path AB 8.5.39 0x33 0x0800 GAINCD Gain for path CD 8.5.40 0x34-0x40 0x0000 Reserved Reserved 0x41 0x0000 JESD_ERR_CNT JESD Error Counter 8.5.41 0x42-0x45 0x0000 Reserved Reserved 0x46 0x0044 JESD_ID1 JESD ID 1 8.5.42 0x47 0x190A JESD_ID2 JESD ID 2 8.5.43 0x48 0x31C3 JESD_ID3 JESD ID 3 and Subclass 8.5.44 0x49 0x0000 Reserved Reserved 0x4A 0x0003 JESD_LN_EN JESD Lane Enable 8.5.45 0x4B 0x1300 JESD_RBD_F JESD RBD Buffer and Frame Octets 8.5.46 |
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