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the inverse of EOC, plus or minus a few ns of gate delay. To use

an external GLCK and OCLK, determine the phase of the exter-

nal OCLK and GLCK with respect to EOC. Then look at Diagrams

18 and 19 (2 bus mode) or 20 and 21 (1 bus mode). Choose a

phase setting (0° or 180°, register 26 bits 6 and 7) for OCLK and

GCLK that provides the most margin with respect to the tOCLK-

EOC1 (OCLK IN), tOCLK-EOC2 (OCLK IN), and tGCLK-EOC (GCLK IN)

specifications.

It is entirely possible that either setting (0° or 180°) will work

equally well. The condition that must be avoided is when FF3 is

clocked (falling edge of EOC) at the same time the input data to

FF3 is changing (rising edge of OCLK/GCLK for 0° phase, or fall-

ing edge of OCLK/GCLK for 180° phase). As long as this does

not occur simultaneously, the data will be correctly latched.

Note that the coefficient data must appear sooner (relative to the

pixel output data) for the Clock In modes, to account for the extra

latency through FF1 and FF2. This additional time is shown in

Diagrams 18 through 21.

This mode of operation may seem confusing at first, but it is nec-

essary to allow the synchronous LM9812 to phase lock to exter-

nal coefficient data of unknown phase.

1.5.4 MCLK

This is the master clock input for the LM9812. The ADC conver-

sion rate is fixed at 1/4 of this frequency. The pixel rate in 3 chan-

nel mode is 1/12 of the MCLK frequency. Many of the timing

parameters are also relative to the frequency of this clock.

1.5.5 SYNC

This input signals the beginning of a line. When SYNC goes high,

the LM9812 generates a TR pulse, then begins converting pixels

until the SYNC line is brought low again. If SYNC is externally

applied, the LM9812 will work with sensors with any number of

pixels. If SYNC is internally generated (in combination with the

RUN/STOP input), sensors with up to 3 channels of 16383 pix-

els/channel can be used.

1.5.6 RUN/STOP

The LM9812 has a “SYNC OUT” mode (Register 24, bit 4=1) that

automatically generates a SYNC pulse stream based on the num-

ber of active pixels and the number of additional end-of-line inte-

gration pixels programmed into registers 12-15. When the

RUN/STOP pin is brought high, the LM9812 begins generating

the periodic SYNC pulse. When RUN/STOP goes low, the

LM9812 will continue converting the remaining active pixels, then

SYNC will go low and the part will “idle” until the next rising edge

of RUN/STOP.

Using the SYNC OUT mode provides a simple way to clock the

sensor continuously with a repeatable, user-programmed integra-

tion period. By varying the number of end-of-line integration pix-

els (in registers 14 and 15), the integration time (and thus the

amplitude of the output signal from the sensor) can be adjusted

with very high accuracy (about 1 part in 5400, or 0.02%, for a

600dpi sensor).

2.0 PREVIEW MODE OPERATION

The LM9812 supports two “preview” or low resolution modes for

CCD sensors (this mode will not work for CIS sensors). In these

modes, adjacent pixels are averaged together in the analog

domain and converted at the maximum ADC conversion rate.

This allows the CCD data to be clocked out and digitized 2 or 4

times faster (corresponding to a 2 to 4 times faster image scan).

The image will be 1/2 or 1/4 the resolution. For example, a 600dpi

sensor will look like a 300dpi sensor in the x2 preview mode, or a

150dpi sensor in the x4 preview mode. This is useful because it

allows faster scans for lower resolution images and scan preview

images. The quality of the lower resolution image is also signifi-

cantly improved because this technique

averages pixels to

reduce the resolution instead of discarding pixels (which often

results in a loss of image information).

In the x2 preview mode, the Ø clock is clocked at 2 times the nor-

mal Ø clock frequency, while the RS pulse stays at the ADC’s

conversion rate. By skipping every other RS pulse, the charge for

pixel n+1 will be added to the charge for pixel n on the CCD itself.

Since the CCD is being clocked at 2 times the normal rate, the

period between lines (and therefore the integration time) will be

half as long, causing the amplitude of each pixel to be half as

large. Since the output of the CCD is the sum of two pixels, the

final amplitude seen by the LM9812 is very similar to what it is in

normal mode. The final pixel amplitude will be equal to (pn/2 +

pn+1/2) = (pn + pn+1)/2 = the average of pn and pn+1.

The same principle applies in the x4 preview mode. Here the Ø

clock is clocked at 4 times the normal Ø clock frequency, while

the RS pulse stays at the ADC’s conversion rate. By skipping 3

out of 4 RS pulses, the charge for pixels n, n+1, n+2, and n+3 will

be averaged in the CCD’s output stage. Since the CCD is being

clocked at 4 times the normal rate, the period between lines (and

therefore the integration time) will be one quarter as long. The

final pixel amplitude will be equal to (pn + pn+1+ pn+2+ pn+3)/4 =

the average of pn, pn+1, pn+2, and pn+3.

Getting the optimum performance out of the preview modes with

a particular CCD may require adjusting the RS pulse width, RS

pulse position, Sample Reference, and Sample Signal timing

(Registers 21, 22, and 23).

CDS

(Internal)

Diagram 4: x2 Preview Mode Timing

Hold Ref

Hold Signal

Ø1

(Even/Odd Mode)

Ø2

(Even/Odd Mode)

Ø1

(Standard Mode)

Ø2

(Standard Mode)

pn+1

1.5 1.5

All lengths given in units of MCLK periods

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