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ADT7516/ADT7517/ADT7519

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LDAC Configuration Register (Write-Only) [Add. = 1Ch]

This configuration register is an 8-bit write register that is used

to control the updating of the quad DAC outputs if the LDAC

pin is disabled and Bits D4:D5 of the DAC configuration reg-

ister are both set to 1. Also selects either the internal or external

VREF for all four DACs. Bits D0:D3 in this register are self-clear-

ing, i.e., reading back from this register will always give 0s for

these bits.

Table 45. LDAC Configuration

*Default settings at power-up.

Table 46.

Bit

Function

Writing a 1 to this bit will generate the LDAC command

to update DAC A output only.

Writing a 1 to this bit will generate the LDAC command

to update DAC B output only.

Writing a 1 to this bit will generate the LDAC command

to update DAC C output only.

Writing a 1 to this bit will generate the LDAC command

to update DAC D output only.

Selects either internal VREF or external VREF for DACs A

and B.

0 = External VREF

1 = Internal VREF.

Selects either internal VREF or external VREF for DACs C

and D.

0 = External VREF

1 = Internal VREF

D6:D7

Reserved. Write 0s only.

Interrupt Mask 1 Register (Read/Write) [Add. = 1Dh]

This mask register is an 8-bit read/write register that can be

used to mask any interrupts that can cause the INT/INT pin to

go active.

Table 47. Interrupt Mask 1

*Default settings at power-up.

Table 48.

Bit

Function

0 = Enable internal THIGH interrupt.

1 = Disable internal THIGH interrupt.

0 = Enable internal TLOW interrupt.

1 = Disable internal TLOW interrupt.

0 = Enable external THIGH interrupt or AIN1 interrupt.

1 = Disable external THIGH interrupt or AIN1 interrupt.

0 = Enable external TLOW interrupt.

1 = Disable external TLOW interrupt.

0 = Enable external temperature fault interrupt.

1 = Disable external temperature fault interrupt.

0 = Enable AIN2 interrupt.

1 = Disable AIN2 interrupt.

0 = Enable AIN3 interrupt.

1 = Disable AIN3 interrupt.

0 = Enable AIN4 interrupt.

1 = Disable AIN4 interrupt.

Interrupt Mask 2 Register (Read/Write) [Add. = 1Eh]

This mask register is an 8-bit read/write register that can be

used to mask any interrupts that can cause the INT/INT pin to

go active.

Table 49. Interrupt Mask 2

*Default settings at power-up.

Table 50.

Bit

Function

D0:D3

Reserved. Write 0s only.

0 = Enable VDD interrupts.

1 = Disable VDD interrupts.

D5:D7

Reserved. Write 0s only.

Internal Temperature Offset Register (Read/Write)

[Add. = 1Fh]

This register contains the offset value for the internal temp-

erature channel. A twos complement number can be written to

this register which is then added to the measured result before it

is stored or compared to limits. In this way, a one-point cali-

bration can be done whereby the whole transfer function of the

channel can be moved up or down. From a software point of

view, this may be a very simple method to vary the charac-

teristics of the measurement channel if the thermal charac-

teristics change. Because it is an 8-bit register, the temperature

resolution is 1°C.

Table 51. Internal Temperature Offset

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