COP884CG datasheet(22/42 Pages) NSC

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Comparators (Continued)

CMPSL REGISTER (ADDRESS X’00B7)

The CMPSL register contains the following bits

CMP1EN Enable comparator 1

CMP1RD Comparator 1 result (this is a read only bit

which will read as 0 if the comparator is not

enabled)

CMP10E

Selects pin I3 as comparator 1 output provided

that CMPIEN is set to enable the comparator

CMP2EN

Enable comparator 2

CMP2RD

Comparator 2 result (this is a read only bit

which will read as 0 if the comparator is not

enabled)

CMP20E

Selects pin I6 as comparator 2 output provided

that CMP2EN is set to enable the comparator

Unused CMP20E CMP2RD CMP2EN CMP10E CMP1RD CMP1EN Unused

Bit 7

Bit 0

Note that the two unused bits of CMPSL may be used as

software flags

Comparator outputs have the same spec as Ports L and G

except that the rise and fall times are symmetrical

Interrupts

The device supports a vectored interrupt scheme It sup-

ports a total of fourteen interrupt sources The following ta-

ble lists all the possible device interrupt sources their arbi-

tration ranking and the memory locations reserved for the

interrupt vector for each source

Two bytes of program memory space are reserved for each

interrupt source All interrupt sources except the software

interrupt are maskable Each of the maskable interrupts

have an Enable bit and a Pending bit A maskable interrupt

is active if its associated enable and pending bits are set If

GIE e 1 and an interrupt is active then the processor will

be interrupted as soon as it is ready to start executing an

instruction except if the above conditions happen during the

Software Trap service routine This exception is described

in the Software Trap sub-section

The interruption process is accomplished with the INTR in-

struction (opcode 00) which is jammed inside the Instruc-

tion Register and replaces the opcode about to be execut-

ed The following steps are performed for every interrupt

1 The GIE (Global Interrupt Enable) bit is reset

2 The address of the instruction about to be executed is

pushed into the stack

3 The PC (Program Counter) branches to address 00FF

This procedure takes 7 tc cycles to execute

TLDD9765 – 22

FIGURE 15 Interrupt Block Diagram

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