COP884CG datasheet(10/42 Pages) NSC

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Control Registers (Continued)

PSW Register (Address X 00EF)

The PSW register contains the following select bits

GIE

Global interrupt enable (enables interrupts)

EXEN

Enable external interrupt

BUSY

MICROWIREPLUS busy shifting flag

EXPND

External interrupt pending

T1ENA

Timer T1 Interrupt Enable for Timer Underflow

or T1A Input capture edge

T1PNDA Timer T1 Interrupt Pending Flag (Autoreload RA

in mode 1 T1 Underflow in Mode 2 T1A cap-

ture edge in mode 3)

Carry Flag

Half Carry Flag

C T1PNDA T1ENA EXPND BUSY EXEN GIE

Bit 7

Bit 0

The Half-Carry bit is also affected by all the instructions that

affect the Carry flag The SC (Set Carry) and RC (Reset

Carry) instructions will respectively set or clear both the car-

ry flags In addition to the SC and RC instructions ADC

SUBC RRC and RLC instructions affect the carry and Half

Carry flags

ICNTRL Register (Address X 00E8)

The ICNTRL register contains the following bits

T1ENB

Timer T1 Interrupt Enable for T1B Input capture

edge

T1PNDB Timer T1 Interrupt Pending Flag for T1B cap-

ture edge

WEN

Enable MICROWIREPLUS interrupt

WPND MICROWIREPLUS interrupt pending

T0EN

Timer T0 Interrupt Enable (Bit 12 toggle)

T0PND

Timer T0 Interrupt pending

LPEN

L Port Interrupt Enable (Multi-Input WakeupIn-

terrupt)

Bit 7 could be used as a flag

Unused LPEN T0PND T0EN mWPND mWEN T1PNDB T1ENB

Bit 7

Bit 0

T2CNTRL Register (Address X 00C6)

The T2CNTRL register contains the following bits

T2ENB

Timer T2 Interrupt Enable for T2B Input capture

edge

T2PNDB Timer T2 Interrupt Pending Flag for T2B cap-

ture edge

T2ENA

Timer T2 Interrupt Enable for Timer Underflow

or T2A Input capture edge

T2PNDA Timer T2 Interrupt Pending Flag (Autoreload RA

in mode 1 T2 Underflow in mode 2 T2A cap-

ture edge in mode 3)

T2C0

Timer T2 StartStop control in timer modes 1

and 2 Timer T2 Underflow Interrupt Pending

Flag in timer mode 3

T2C1

Timer T2 mode control bit

T2C2

Timer T2 mode control bit

T2C3

Timer T2 mode control bit

T2C3 T2C2 T2C1 T2C0 T2PNDA T2ENA T2PNDB T2ENB

Bit 7

Bit 0

T3CNTRL Register (Address X 00B6)

The T3CNTRL register contains the following bits

T3ENB

Timer T3 Interrupt Enable for T3B

T3PNDB Timer T3 Interrupt Pending Flag for T3B pin

(T3B capture edge)

T3ENA

Timer T3 Interrupt Enable for Timer Underflow

or T3A pin

T3PNDA Timer T3 Interrupt Pending Flag (Autoload RA

in mode 1 T3 Underflow in mode 2 T3a cap-

ture edge in mode 3)

T3C0

Timer T3 StartStop control in timer modes 1

and 2

Timer T3 Underflow Interrupt Pending Flag in

timer mode 3

T3C1

Timer T3 mode control bit

T3C2

Timer T3 mode control bit

T3C3

Timer T3 mode control bit

T3C3

T3C2

T3C1

T3C0 T3PNDA T3ENA T3PNDB T3ENB

Bit 7

Bit 0

Timers

The device contains a very versatile set of timers (T0 T1

T2 T3) All timers and associated autoreloadcapture regis-

ters power up containing random data

TIMER T0 (IDLE TIMER)

The device supports applications that require maintaining

real time and low power with the IDLE mode This IDLE

mode support is furnished by the IDLE timer T0 which is a

16-bit timer The Timer T0 runs continuously at the fixed

rate of the instruction cycle clock tc The user cannot read

or write to the IDLE Timer T0 which is a count down timer

The Timer T0 supports the following functions

Exit out of the Idle Mode (See Idle Mode description)

WATCHDOG logic (See WATCHDOG description)

Start up delay out of the HALT mode

The IDLE Timer T0 can generate an interrupt when the thir-

teenth bit toggles This toggle is latched into the T0PND

pending flag and will occur every 4 ms at the maximum

clock frequency (tc e 1 ms) A control flag T0EN allows the

interrupt from the thirteenth bit of Timer T0 to be enabled or

disabled Setting T0EN will enable the interrupt while reset-

ting it will disable the interrupt

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