M21050 datasheet(18/70 Pages) MA-COM

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Mindspeed Technologies™

21050-DSH-001-F

Mindspeed Proprietary and Confidential

M21050 Data Sheet

By default, the loop bandwidth is set at an approximate bandwidth of 8 MHz, with DRD = 1 and Fvco = 2.5 GHz.

Within a given VCO frequency range, the bandwidth will scale proportionately. For example, if the loop bandwidth

(FLBW) is 8 MHz at 2.5 GHz, then at 3.125 GHz the FLBW will be 10 MHz. When DRD is not equal to 1, the band-

width at DRD = 1 scales by the DRD divide ratio. For example, if the FLBW is 8 MHz at Fvco = 2.5 GHz with DRD =

1, then if DRD = 2, Fvco = 1.25 GHz and the FLBW will be 4 MHz. In the hardwired mode, the FLBW will be properly

set for the hardwired data-rates. In the two-wire interface mode, the default bandwidth scales automatically with the

input data-rate, and the bandwidth can be tuned through the registers.

The CDR needs to achieve frequency lock before it can achieve phase lock and re-time the input data. Frequency

reference acquisition (FRA) requires an external frequency source to be connected to the RefClk [P/N] pins.

Frequency acquisition is accomplished with two key sections. The first section is a secondary frequency lock loop

(FLL) that drives the VCO towards the desired frequency. The second section is the loss-of-lock circuitry (LOLCir),

that turns on or off the secondary FLL. In general, both LOL and LOA have register bits (Alarm_LOA and

Alarm_LOL) which are active high, and pins (xAlarmA and xAlarmB) which are active low. The pin xAlarmA

(xAlarmB) is an internal wired OR of the four LOL and four LOA alarms associated with the four CDRs in block

A(B). xAlarmA and xAlarmB can be wired OR externally. In the general context, they will be referred to as LOL or

LOA which is active H. Frequency acquisition takes place when the LOLCir determines an out of lock condition

(LOL = H) for each CDR, when the VCO frequency exceeds a given range (window). LOLCir enables the second-

ary FLL to drive the VCO close to the desired frequency (typically the signal data-rate). When the VCO falls within

a given frequency range where the CDR loop can acquire phase lock, LOLCir turns off the secondary FLL and sets

LOL = L, allowing the CDR to achieve phase lock. During this time, LOLCir continues to monitor the frequency dif-

ference and will signal a LOL = H, to start the acquisition routine again, if the frequency falls out of range. The LOL-

Cir range is fixed in the hardwired mode, and programmable in the two-wire interface mode. The frequency

threshold (window) for LOL = H-to-L and LOL = L-to-H are different, to prevent LOL from toggling when the fre-

quency is near one of the windows. These registers also control the frequency acquisition time. Suggested values

are given in this document for general robust operation, and are used as register defaults, however, the program-

mability of the registers allow for optimization based on a given application (e.g. faster lock times).

Each CDR contains an independent loss of activity (LOA) detector that determines if there is valid data, by looking

at the transition density of the reference clock. Fixed window detectors compare the data transition density with the

reference clock. If the data transition density falls outside of the window, a loss of activity condition is signaled.

When LOA goes high, it also (just like LOL) forces the FLL to turn on, so that the VCO will be forced to the desired

frequency range. When LOA goes low again, phase lock will occur.

All of the CDRs are reset upon xRST = L, Mastreset = AAh, or upon power up. A soft reset through

CDR_ctrlA_N[7] = 1b resets the individual CDR state machine, and presets the CDR to an out-of-lock condition,

however, the register contents that are related to CDR setup are unchanged. It is required to force a soft reset if the

data-rate is dynamically changed. The soft reset register bit needs to be cleared for proper operation. A reset dur-

ing operation will cause bit errors, until the CDR achieves phase lock.

By default, all of the CDRs are active and powered up for normal operation. By setting CDR_ctrlB_N[7:6] = 11b, a

CDR can be bypassed and powered down, to allow for non-standard data-rates, or to save power when the CDR is

not required at lower data-rates. When CDR_ctrlB_N[7:6] = 01b, the CDR is bypassed so the output data is not re-

timed but active (VCO locked to the input data). In the last mode with CDR_ctrlB_N[7:6] = 10b, the CDR is powered

down, and all signals along the input and output paths are also powered down, to save power. In this case, the

input data does not reach the output.

The internal loop filter automatically scales with the VCO data rate divider selection. For operation with the VCO

tuning range for a fixed DRD setting, the loop bandwidth scales proportionally for the new data-rate. The loop band-

width can be selected with Phadj_ctrl_N[5:4], and the 400% setting with Phadj_ctrl_N[5:4] = 10b is the default.

To prevent the propagation of noise in the case where there is a LOL/LOA condition, the CDR contains an auto-

inhibit feature, which is enabled by default. When either LOA or LOL is active, the output of the CDR is fixed at a

logic high state (DoutP = H, DoutN = L). This feature can be disabled by setting CDR_ctrlA_N[3] = 0b, which

allows CDR_ctrlA_N[5] to either force an inhibit (1b) or to never inhibit (0b).

M21050 Datasheet(PDF) 18 Page - M/A-COM Technology Solutions, Inc.

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