M21050 datasheet(33/70 Pages) MA-COM

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Registers

21050-DSH-001-F

Mindspeed Technologies™

Mindspeed Proprietary and Confidential

2.1.10

Built In Self-Test (BIST) Receiver Main Control Register

2.1.11

Built In Self-Test (BIST) Receiver Bit Error Counter

Table 2-10. Built In Self-Test (BIST) Receiver Main Control Register (BISTrx_ctrl: Address 11h)

Bits

Type

Default

Label

Description

R/W

MSPD internal

N/A

R/W

rx_ctrclr

Clear the BIST Rx error count register, BISTrx_error (active when

BISTrx_ctrl [1] = 1)

0b: Normal operation

1b: Clear register

5:2

R/W

0000b

rx_patt

Selects the BIST Rx test pattern (active when BISTrx_ctrl [1] = 1)

0000b: PRBS 27-1

0001b: PRBS 215-1

0010b: PRBS 223-1

0011b: PRBS 231-1

0100b: Fibre channel CJTPAT

0101b: Fibre channel CRPAT

0110b: 8b/10b countdown pattern

0111b: 16 bit user programmable pattern

1000b: 20 bit user programmable pattern

R/W

en_rx

Powers up the BIST Rx

0b: Power down

1b: Power up and enable

R/W

rx_rst

Resets the BIST Rx (recommended after powerup/enable, active when

BISTrx_ctrl [1] = 1)

0b: Normal BIST Rx operation

1b: Reset of BIST Rx

Table 2-11. Built In Self-Test (BIST) Receiver Bit Error Counter (BISTrx_error: Address 12h)

Bits

Type

Default

Label

Description

7:0

R/W

00000000b

err

Bit error count (active when BISTrx_ctrl [1] = 1).

This register is set to 00h upon reset, and is incremented for every bit

error the BIST Rx receives, up to FFh. At FFh, the register will stay at

this level until cleared.

M21050 Datasheet(PDF) 33 Page - M/A-COM Technology Solutions, Inc.

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