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M21050 Datasheet(PDF) 29 Page - M/A-COM Technology Solutions, Inc.

Part # M21050
Description  Duplex Quad (Octal) Multi-Rate CDR (1.0 Gbps - 3.2 Gbps)
PDF  70 Pages
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Manufacturer  MA-COM [M/A-COM Technology Solutions, Inc.]
Direct Link  http://www.macomtech.com
Logo MA-COM - M/A-COM Technology Solutions, Inc.

M21050 Datasheet(HTML) 29 Page - M/A-COM Technology Solutions, Inc.

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21050-DSH-001-F
Mindspeed Technologies™
21
Mindspeed Proprietary and Confidential
2.0 Registers
Table 2-1.
Register Table Summary
Addr
Register Name
d7: MSB
d6
d5
d4
d3
d2
d1
d0: LSB
Common Registers
00h
Globctrl
powerup
MSPD int
MSPD int
MSPD int
MSPD int
MSPD int
reserved
clear_alm
03h
Loopback
reserved
reserved
reserved
reserved
loopback[3]
loopback[2]
loopback[1]
loopback[0]
04h
Refclk_ctrl
reserved
reserved
reserved
reserved
ref_divr[2]
ref_divr[1]
ref_divr[0]
MSPD int
05h
Mastreset
rst
rst
rst
rst
rst
rst
rst
rst
06h
Chipcode
chipcode[7]
chipcode[6]
chipcode[5]
chipcode[4]
chipcode[3]
chipcode[2]
chipcode[1]
chipcode[0]
07h
Revcode
revcode[7]
revcode[6]
revcode[5]
revcode[4]
revcode[3]
revcode[2]
revcode[1]
revcode[0]
08h
Input_hys
reserved
reserved
en_hys
reserved
reserved
reserved
reserved
reserved
10h
BISTrx_chsel
reserved
chan[2]
chan[1]
chan[0]
11h
BISTrx_ctrl
MSPD int
rx_ctrclr
rx_patt[3]
rx_patt[2]
rx_patt[1]
rx_patt[0]
en_rx
rx_rst
12h
BISTrx_error
err[7]
err[6]
err[5]
err[4]
err[3]
err[2]
err[1]
err[0]
14h
BISTtx_chsel
tx_chan_7
tx_chan_6
tx_chan_5
tx_chan_4
tx_chan_3
tx_chan_2
tx_chan_1
tx_chan_0
15h
BISTtx_ctrl
err_insert
rx2txclk
tx_patt[3]
tx_patt[2]
tx_patt[1]
tx_patt[0]
en_tx
tx_rst
17h
BISTtx_LOLctrl
tacq_LOL[2]
tacq_LOL[1]
tacq_LOL[0]
narwin_LOL[3]
narwin_LOL[2]
narwin_LOL[1]
narwin_LOL[0]
widwin_LOL[0]
18h
BISTtx_PLL_ctrlA
softreset
MSPD int
reserved
MSPD int
reserved
MSPD int
reserved
MSPD int
19h
BISTtx_PLL_ctrlB
PLLmode[1]
PLLmode[0]
MSPD int
MSPD int
data_rate[3]
data_rate[2]
data_rate[1]
data_rate[0]
1Ah
BISTtx_PLL_ctrlC
VCO_divr[7]
VCO_divr[6]
VCO_divr[5]
VCO_divr[4]
VCO_divr[3]
VCO_divr[2]
VCO_divr[1]
VCO_divr[0]
1Bh
BIST_pattern0
pattern[19]
pattern[18]
pattern[17]
pattern[16]
1Ch
BIST_pattern1
pattern[15]
pattern[14]
pattern[13]
pattern[12]
pattern[11]
pattern[10]
pattern[9]
pattern[8]
1Dh
BIST_pattern2
pattern[7]
pattern[6]
pattern[5]
pattern[4]
pattern[3]
pattern[2]
pattern[1]
pattern[0]
1Fh
BISTtx_alarm
tx_LOL
reserved
reserved
MSPD int
MSPD int
MSPD int
MSPD int
MSPD int
20h
Temp_mon
reserved
reserved
en_temp_mon
strobe_temp
21h
Temp_value
temp[3]
temp[2]
temp[1]
temp[0]
30h
Alarm_LOL
LOL_7
LOL_6
LOL_5
LOL_4
LOL_3
LOL_2
LOL_1
LOL_0
31h
Alarm_LOA
LOA_7
LOA_6
LOA_5
LOA_4
LOA_3
LOA_2
LOA_1
LOA_0
Per channel registers (N = channel/CDR#, M = N+4)
M0h
CDR_ctrlA_N
softreset
MSPD int
inh_force
MSPD int
autoinh_en
MSPD int
LOA_en
MSPD int
M1h
CDR_ctrlB_N
CDRmode[1]
CDRmode[0]
MSPD int
reserved
data_rate[3]
data_rate[2]
data_rate[1]
data_rate[0]
M2h
CDR_ctrlC_N
VCO_divr[7]
VCO_divr[6]
VCO_divr[5]
VCO_divr[4]
VCO_divr[3]
VCO_divr[2]
VCO_divr[1]
VCO_divr[0]
M3h
Out_ctrl_N
outlvl[1]
outlvl[0]
reserved
reserved
data_pol_flip
dataout_en
MSPD int
MSPD int
M4h
Preemp_ctrl_N
reserved
MSPD int
MSPD int
MSPD int
MSPD int
preemph[2]
preemph[1]
preemph[0]
M5h
Ineq_ctrl_N
reserved
MSPD int
MSPD int
en_DCservo
in_eq[2]
en_ad_eq
in_eq[1]
in_eq[0]
M6h
Phadj_ctrl_N
i_trim[1]
i_trim[0]
r_sel[1]
r_sel[0]
phase_adj[3]
phase_adj[2]
phase_adj[1]
phase_adj[0]
M9h
LOL_ctrl_N
tacq_LOL[2]
tacq_LOL[1]
tacq_LOL[0]
narwin_LOL[3]
narwin_LOL[2]
narwin_LOL[1]
narwin_LOL[0]
widwin_LOL[0]
MAh
Jitter_reduc_N
MSPD int
MSPD int
lowjitter
MSPD int
MSPD int
MSPD int
MSPD int
MSPD int
Notes:
1. N = 0 for channel/CDR A0, N = 1 for channel/CDR A1,..., N = 7 for channel/CDR B3.
2. M = 4h for channel/CDR A0, M = 5h for channel/CDR A1,..., M = Bh for channel/CDR B3. For example channel/CDR A0 starts at address 40h, channel/CDR A1 at 50h, channel/
CDR A2 at 60h, channel/CDR A3 at 70h, channel/CDR B0 at 80h, channel/CDR B1 at 90h, channel/CDR B2 at A0h, channel/CDR B3 at B0h.



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