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PC87307 Datasheet(PDF) 53 Page - National Semiconductor (TI) |
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PC87307 Datasheet(HTML) 53 Page - National Semiconductor (TI) |
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53 / 218 page  53 Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2) www.national.com A-B Update In Progress (UIP) bit high before update occurs = 244 µsec D-C Periodic interrupt to update = Period (periodic int) / 2 + 244 µsec C-E Update to Alarm Interrupt = 30.5 µs UIP Update In Progress status bit UF Update-Ended Interrupt Flag (Update-Ended Interrupt if enabled) PF Periodic Flag (Periodic Interrupt if enabled) AF Alarm Flag (Alarm Interrupt if enabled) Flags (and IRQ) are reset at the conclusion of Control Register C (CRC) read or by reset. UIP bit of CRA UF bit of CRC PF bit of CRC AF bit of CRC A B C D E FIGURE 4-5. Interrupt/Status Timing TABLE 4-2. Periodic Interrupt Rate Encoding RS3-0 3 2 1 0 Periodic Interrupt Rate 0 0 0 0 none 0 0 0 1 3.90625 msec 0 0 1 0 7.8125 msec 0 0 1 1 122.070 µsec 0 1 0 0 244.141 µsec 0 1 0 1 488.281 µsec 0 1 1 0 976.562 µsec 0 1 1 1 1.953125 msec 1 0 0 0 3.90625 msec 1 0 0 1 7.8125 msec 1 0 1 0 15.625 msec 1 0 1 1 31.25 msec 1 1 0 0 62.5 msec 1 1 0 1 125 msec 1 1 1 0 250 msec 1 1 1 1 500 msec TABLE 4-3. Divider Chain Control and Bank Selection a. The oscillator stops in this case only in the event of a power failure. DV2-0 6 5 4 Selected Bank Configuration 0 0 0 Bank 0 Oscillator Disableda 0 0 1 Bank 0 Oscillator Disableda 0 1 0 Bank 0 Normal Operation 0 1 1 Bank 1 Normal Operation 1 0 0 Bank 2 Normal Operation 1 0 1 Undefined Test 1 1 0 Bank 0 Divider Chain Reset 1 1 1 Bank 0 Divider Chain Reset |
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