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SC2200 Datasheet(PDF) 333 Page - National Semiconductor (TI) |
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SC2200 Datasheet(HTML) 333 Page - National Semiconductor (TI) |
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333 / 433 page  Revision 3.0 333 www.national.com Video Processor Module (Continued) 6.2.7 Integrated PLL The integrated (CRT) PLL can generate frequencies up to 135MHz from asingle27MHz source.The clockfre- quency is programmable using two registers. Figure 6-15 shows the block diagram of the Video Processor integrated PLL. FREF is 27 MHz, generated by an external crystal and an integrated oscillator. FOUT is calculated from: FOUT = (m + 1) / (n+ 1) x FREF The integrated PLL can generate any frequency by writing into the CRT-m and CRT-n bit fields (FBAR0+Memory Off- set 2Ch). Additionally, 16 preprogrammed VGA frequencies can be selected via the PLL Clock Select register (F4BAR0+Memory Offset 2Ch[19:16]), if the crystal oscilla- tor has a frequency of 27 MHz. This PLL can be powered down via the Miscellaneous register (F4BAR0+Memory Offset 28h[12]). Figure 6-15. PLL Block Diagram FREF FOUT n Phase Charge m VCO Compare Divider Divider Pump Loop Filter Out Divide |
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