DS1963S datasheet(12/37 Pages) DALLAS

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DS1963S

12 of 37

Memory and SHA Function Flow Chart Figure 7

Spare

Vertical

F0h

Read Memory

TA1(T7:T0), TA2 (T15:T8)

Bus Master TX

CHLG = 0 ; AUTH = 0

Address

< 2B0h ?

Address = (T15:T0)

DS1963S sets Memory

3Ch

Match Scratch-

pad

CHLG = 0 ; MATCH = 0

SP Offset = 27

DS1963S sets Scratch-

pad Offset = 8 decimal

DS1963S TX "1"

Master

TX Reset ?

Master

TX Reset ?

increments

DS1963S

SP. Offset

Bus Master TX Memory or

SHA Function Command

From ROM Functions

Flow Chart (Figure 10)

To ROM Functions

Flow Chart (Figure 10)

To Figure 7

2nd Part

From Figure 7

2nd Part

Bus Master

RX "1"s

Address

< 2AFh ?

Master

TX Reset ?

Bus Master

RX "1"s

increments

DS1963S

Address

Counter

Data Byte from

Bus Master RX

Memory Address

Master

TX Reset ?

Bus Master RX

FFh byte

Pages

16 to 17 ?

AUTH=1?

DS1963S TX "0"

DS1963S TX CRC16 of

Command and Data

AUTH=0; MATCH=1

Bus Master TX

data byte

Data Bytes

Match ?

DS1963S Datasheet(PDF) 12 Page - Dallas Semiconductor

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