DS1963S

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1-WIRE BUS SYSTEM

The 1-Wire bus is a system that has a single bus master and one or more slaves. In all instances the

DS1963S is a slave device. The bus master is typically a microcontroller or PC. For small configurations

the 1-Wire communication signals can be generated under software control using a single port pin. For

multisensor networks, the DS2480B 1-Wire line driver chip or serial port adapters based on this chip

(DS9097U series) are recommended. This simplifies the hardware design and frees the microprocessor

from responding in real-time.

The discussion of this bus system is broken down into three topics: hardware configuration, transaction

sequence, and 1-Wire signaling (signal types and timing). The 1-Wire protocol defines bus transactions in

terms of the bus state during specific time slots that are initiated on the falling edge of sync pulses from

the bus master. For a more detailed protocol description, refer to Chapter 4 of the Book of DS19xx iButton

Standards.

HARDWARE CONFIGURATION

The 1-Wire bus has only a single line by definition; it is important that each device on the bus be able to

drive it at the appropriate time. To facilitate this, each device attached to the 1-Wire bus must have open

drain or tri-state outputs. The 1-Wire port of the DS1963S is open-drain with an internal circuit

equivalent to that shown in Figure 9.

A multidrop bus consists of a 1-Wire bus with multiple slaves attached. At standard speed the 1-Wire bus

has a maximum data rate of 16.3kbits per second. The speed can be boosted to 142kbits per second by

activating the Overdrive mode. The DS1963S is not guaranteed to be fully compliant to the iButton

Standard. Its maximum data rate in standard speed mode is 15.4kbits per second and 125kbits per second

in Overdrive. The value of the pullup resistor primarily depends on the network size and load conditions.

For most applications the maximum value of 2.2k

W will be adequate.

The idle state for the 1-Wire bus is high. If for any reason a transaction needs to be suspended, the bus

must be left in the idle state if the transaction is to resume. If this does not occur and the bus is left low

for more than 16µs (Overdrive speed) or more than 120µs (standard speed), one or more devices on the

bus may be reset. With the DS1963S the bus must be left low for no longer than 15.4µs at Overdrive

speed to ensure that none of the slave devices on the 1-Wire bus performs a reset. Despite of its limited

compliance, the DS1963S will communicate properly when used in conjunction with a DS2480B 1-Wire

driver and serial port adapters that are based on this driver chip.

HARDWARE CONFIGURATION Figure 9

Open Drain

Port Pin

RX = RECEIVE

TX = TRANSMIT

100 W

MOSFET

RX

TX

TX

RX

DATA

SEE

TEXT

5 µA

Typ.

BUS MASTER

DS1963S 1-Wire PORT