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HT45F56 Datasheet(PDF) 59 Page - Holtek Semiconductor Inc |
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HT45F56 Datasheet(HTML) 59 Page - Holtek Semiconductor Inc |
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59 / 90 page  Rev. 1.11 58 April 11, 2017 Rev. 1.11 59 April 11, 2017 HT45F56 Shock Detector Flash MCU HT45F56 Shock Detector Flash MCU Timer/Counter Mode Toselectthismode,bitsCTM1andCTM0intheCTMC1registershouldbesetto11respectively. TheTimer/CounterModeoperatesinanidenticalwaytotheCompareMatchOutputMode generatingthesameinterruptflags.TheexceptionisthatintheTimer/CounterModetheCTM outputpinisnotused.ThereforetheabovedescriptionandTimingDiagramsfortheCompare MatchOutputModecanbeusedtounderstanditsfunction.AstheCTMoutputpinisnotusedin thismode,thepincanbeusedasanormalI/Opinorotherpin-sharedfunction. PWM Output Mode Toselectthismode,bitsCTM1andCTM0intheCTMC1registershouldbesetto10respectively. ThePWMfunctionwithintheCTMisusefulforapplicationswhichrequirefunctionssuchasmotor control,heatingcontrol,illuminationcontroletc.Byprovidingasignaloffixedfrequencybutof varyingdutycycleontheCTMoutputpin,asquarewaveACwaveformcanbegeneratedwith varyingequivalentDCRMSvalues. AsboththeperiodanddutycycleofthePWMwaveformcanbecontrolled,thechoiceofgenerated waveformisextremelyflexible.InthePWMmode,theCTCCLRbithasnoeffectonthePWM operation.BothoftheCCRAandCCRPregistersareusedtogeneratethePWMwaveform,one registerisusedtocleartheinternalcounterandthuscontrolthePWMwaveformfrequency,while theotheroneisusedtocontrolthedutycycle.Whichregisterisusedtocontroleitherfrequency ordutycycleisdeterminedusingtheCTDPXbitintheCTMC1register.ThePWMwaveform frequencyanddutycyclecanthereforebecontrolledbythevaluesintheCCRAandCCRPregisters. Aninterruptflag,oneforeachoftheCCRAandCCRP,willbegeneratedwhenacomparematch occursfromeitherComparatorAorComparatorP.TheCTOCbitintheCTMC1registerisusedto selecttherequiredpolarityofthePWMwaveformwhilethetwoCTIO1andCTIO0bitsareusedto enablethePWMoutputortoforcetheTMoutputpintoafixedhighorlowlevel.TheCTPOLbitis usedtoreversethepolarityofthePWMoutputwaveform. • 10-bit CTM, PWM Mode, Edge-aligned Mode, CTDPX=0 CCRP 001b 011b 011b 100b 101b 110b 111b 000b Period 128 256 384 512 640 768 896 1024 Duty CCRA IffSYS=8MHz,CTMclocksourceisfSYS/4,CCRP=2andCCRA=128, TheCTMPWMoutputfrequency=(fSYS/4)/(2x256)=fSYS/2048=4kHz,duty=128/(2x256)=25%. IftheDutyvaluedefinedbytheCCRAregisterisequaltoorgreaterthanthePeriodvalue,thenthe PWMoutputdutyis100%. • 10-bit CTM, PWM Mode, Edge-aligned Mode, CTDPX=1 CCRP 001b 011b 011b 100b 101b 110b 111b 000b Period CCRA Duty 128 256 384 512 640 768 896 1024 ThePWMoutputperiodisdeterminedbytheCCRAregistervaluetogetherwiththeCTMclock whilethePWMdutycycleisdefinedbytheCCRPregistervalue. |
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