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WM8235 Datasheet(PDF) 51 Page - Cirrus Logic |
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WM8235 Datasheet(HTML) 51 Page - Cirrus Logic |
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51 / 154 page  WM8235 Rev 4.6 51 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R104 (68h) 1:0 AGC_TARGETIN5 [9:8] 00 MSB of AGC target level for IN5 R105 (69h) 7:0 AGC_TARGETIN6 [7:0] 0000_0000 LSB of AGC target level for IN6 R106 (6Ah) 1:0 AGC_TARGETIN6 [9:8] 00 MSB of AGC target level for IN6 R191 (BFh) 7:0 PEAKDET_RISE [7:0] 0000_0000 LSB of PEAKDET_RISE[14:0] peak detection start pixel count R192 (C0h) 6:0 PEAKDET_RISE [14:8] 000_0000 MSB of PEAKDET_RISE[14:0] peak detection start pixel count R193 (C1h) 7:0 PEAKDET_FALL [7:0] 0000_0000 LSB of PEAKDET_FALL[14:0] peak detection start pixel count R194 (C2h) 6:0 PEAKDET_FALL [14:8] 000_0000 MSB of PEAKDET_FALL[14:0] peak detection start pixel count LINE-BY-LINE OPERATION Certain linear sensors give colour output on a line-by-line basis. i.e. a full line of red pixels followed by a line of green pixels followed by a line of blue pixels. The WM8235 can accommodate this type of input by setting the LINEBYLINE register bit high. The offset and gain values that are applied to every input channel can be selected, by internal multiplexers, to come from IN7, IN8 or IN9 offset and gain registers. This allows the gain and offset values for each of the input colours to be setup individually at the start of a scan. When register bit ACYC=0 the gain and offset multiplexers are controlled via the INTM[1:0] register bits. When INTM=00 the IN7 offset and gain control registers are used to control every input channel, INTM=01 selects the IN8 offset and gain registers and INTM=10 selects the IN9 offset and gain registers to control every input channel. When register bit ACYC=1, ‘auto-cycling’ is enabled, and the input channel switches to the next offset and gain registers in the sequence by TGSYNC. The sequence is IN7 IN8 IN9 IN7 … offset and gain registers applied to every input channel. AGAININ7, DGAININ7, DACIN7 AGAININ8, DGAININ8, DACIN8 AGAININ9, DGAININ9, DACIN9 INTM=00 INTM=01 INTM=10 Reserved INTM=11 AGAININ7, DGAININ7, DACIN7 0 AGAININ8, DGAININ8, DACIN8 AGAININ8, DGAININ8, DACIN8 TGSYNC LINEBYLINE 0x23[0] IN1 LINEBYLINE INTM Mode AGAININ1, DGAININ1, DACIN1 AGAININ2, DGAININ2, DACIN2 AGAININ3, DGAININ3, DACIN3 AGAININ4, DGAININ4, DACIN4 AGAININ5, DGAININ5, DACIN5 AGAININ6, DGAININ6, DACIN6 IN2 IN3 IN4 IN5 IN6 Normal Operation Normal Operation INTM 0x23[3:2] 1 00 0 00 01 AGAININ9, DGAININ9, DACIN9 ACYC 0x23[1] INTM Mode (depends on INTM register) Auto Cycling mode (IN7 -> IN8 -> IN9) ACYC=0 ACYC=1 AGAININ1, DGAININ1, DACIN1 AGAININ2, DGAININ2, DACIN2 AGAININ3, DGAININ3, DACIN3 AGAININ4, DGAININ4, DACIN4 AGAININ5, DGAININ5, DACIN5 AGAININ6, DGAININ6, DACIN6 AGAININ7, DGAININ7, DACIN7 AGAININ8, DGAININ8, DACIN8 AGAININ9, DGAININ9, DACIN9 IN7 IN8 IN9 AGAININ7, DGAININ7, DACIN7 AGAININ8, DGAININ8, DACIN8 AGAININ9, DGAININ9, DACIN9 Must be set to 0 01 11 Figure 33 Line-by-Line Operation (ACYC=0, INTM mode) |
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