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WM8235 Datasheet(PDF) 82 Page - Cirrus Logic |
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WM8235 Datasheet(HTML) 82 Page - Cirrus Logic |
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82 / 154 page ![]() WM8235 82 Rev 4.6 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION REFER TO Note: these settings are applicable for the specific conditions. x0 = normal filter x1 = larger resistor to improve PLL cutoff freq (for SSC) 3:2 PLL_PFD_ CTRL[1:0] 10 Control reset delay to improve PFD sensitivity. 00 = 1ns delay 01 = 2.2ns delay 10 = 3.4ns delay (default) 11 = 5.8ns delay 1:0 PLL_CP_ GAIN[1:0] 01 Control Charge Pump current. 00 = 0.5uA 01 = 1uA (default) 10 = 2uA 11 = 4uA Register 1Bh PLL control 2 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION REFER TO R28 (1Ch) PLL divider control 1 6:4 PLL_EXDIV_ SEL[2:0] 001 Select EX DIV ratio. Need to set according to input frequency. See details in “PLL DLL Setup” 000 = 1 001 = 2 010 = 4 011 = 8 100 = 16 101 to 111 = reserved. 3:0 PLL_FBDIV_ SEL[3:0] 0100 Select FB DIV ratio. (ReadOnly) 0000 = 1 0001 = 2 0010 = 3 0011 = 4 0100 = 6 0101 = 8 0110 = 9 0111 = 12 1000 = 18 1001 to 1111 = reserved. Register 1Ch PLL divider control 1 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION REFER TO R29 (1Dh) PLL divider control 2 5:4 PLL_POSTDIV2 _SEL[1:0] 01 Select POST DIV2 ratio. (Read Only) 00 = 1 01 = 2 10 = 4 11 = 6 3:0 PLL_POSTDIV1 _SEL[3:0] 0100 Select POST DIV1 ratio. (Read Only) 0000 = 1 0001 = 2 |
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