WM8235 datasheet(62/154 Pages) CIRRUS

62 / 154 page

WM8235

Rev 4.6

TG PULSE CONFIGURATION

Figure 49 shows the procedure for TG Pulse Configuration. CLK2~CLK8 can be configured as pulse

type output. See

“Sensor Timing Generation” section for details of TG function.

TG enabled: This must be enabled when TG pulse function is used.

Toggle point configuration: Pulse toggle timing is configured by toggle point setting (TP0~TP31).

TP* register consists of toggle point setting bit (TP pixel counter value bit) and enable bit. The enable

bit must be set when TP is used. Unused TP can be disabled, but this must be followed Note-1 as

described below.

PO0~PO7 configuration: PO0~PO7 are internal pulse for CLK pulse output. Pulse toggle timing is

configured by polarity setting register (0x117~0x136 POL*_PO*).

CLK2~6 pulse out configuration: CLK2~CLK6 can select output signal type, clock type or pulse type

by SEL_CK* register bit. This register must be set when pulse output is required.

PO assignment: Internal PO* pulse will be assigned to CLK2~CLK8 pin with this register.

TG Pulse configuration

Line length

configuration

enabled

0xA1,0xA2 LLENGTH

0xA0[0] TG_EN

TG mode

selection

Master mode

0xA0[1] TGMD=1

Slave mode

0xA0[1] TGMD=0

TG enabled

CLK pin

enabled

0xA5 OE_CK*=1

TG signal output

enabled

0xA9 EN_CK*=1

TG output enabled

Toggle point

Configuration (*1)

0xCF~0x10E

TP*, GEN_TP0, EN_TP*

PO0~PO7

configuration

0x117~0x136 POL*_PO*

CLK2~6 pulse out

Configuration

0xAB~0xAD SEL_CK*=1

Pulse configuration

PO assignment

0xAB~0xAE SEL_PCK*

Figure 49 TG Pulse Configuration

Notes:

1. When configure Toggle point (TP), it must be used from TP0 in ascending order. Also, TP pixel

counter value

must be set as TP0<TP1<TP2 …..

WM8235 Datasheet(PDF) 62 Page - Cirrus Logic

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