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WM8235 Datasheet(PDF) 40 Page - Cirrus Logic |
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WM8235 Datasheet(HTML) 40 Page - Cirrus Logic |
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40 / 154 page ![]() WM8235 40 Rev 4.6 TG PULSE WM8235 can be generated 8 TG pulse internally (PO0 – PO7). These pulses are generated by toggle point setting register (TP*) and polarity setting register (POL*_PO*). WM8235 provided up to 32 toggle point by using TP0 to TP31. PO0-PO7 signals can be assigned to CLK2-CLK8 by SEL_PCK* and SEL_CLK* register. TRIGGER DATA WM8235 can implement trigger data in LVDS flag data (S0, S1, S2, S3 and S4). This can be selected from two methods. One is FLAGPIX register, this can be set one pixel by each line. The other is to apply PO* pulse. Figure 24 shows the trigger data implementation timing. CHANNEL ID Also WM8235 can implement channel identification data instead of trigger data. Table 12 shows the matrix of input channel and channel ID. ID[3] ID[2] ID[1] ID[0] IN1 0 0 0 1 IN2 0 0 1 0 IN3 0 0 1 1 IN4 0 1 0 0 IN5 0 1 0 1 IN6 0 1 1 0 IN7 0 1 1 1 IN8 1 0 0 0 IN9 1 0 0 1 Table 12 Channel ID Channel ID can be assigned to flag data (S0, S1, S2, S3 or S4). The following is the example of channel ID assignment. Example: Assigned channel ID to flag data as ID[3]=S0, ID[2] =S1, ID[1]=S2, ID[0]=S3. If output data is as follows, channel ID will be IN1. (i.e. ID[3]=S0=0, ID[2]=S1=0, ID[1]=S2=0, ID[0]=S3=1) A D5 S0 S1 S2 IN1[0] IN1[1] IN1[2] IN1[3] D4 IN1[4] IN1[5] IN1[6] IN1[7] IN1[8] IN1[9] S3 D3 S4 IN2[0] IN2[1] IN2[2] IN2[3] IN2[4] IN2[5] D2 IN2[6] IN2[7] IN2[8] IN2[9] IN3[0] IN3[1] IN3[2] D1 IN3[3] IN3[4] IN3[5] IN3[6] IN3[7] IN3[8] IN3[9] DCLK H H L L L H H |
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