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WM8235 Datasheet(PDF) 107 Page - Cirrus Logic |
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WM8235 Datasheet(HTML) 107 Page - Cirrus Logic |
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107 / 154 page ![]() WM8235 Rev 4.6 107 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION REFER TO 1 = inverted 1 INV_CLK2 0 invert signal output assigned to CLK2 0 = non-inverted 1 = inverted 0 INV_CLK1 0 invert signal output assigned to CLK1 0 = non-inverted 1 = inverted Register A7h TG config 8 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION REFER TO R169 (A9h) TG config 10 7 EN_CLK8 0 enable signal output CLK8 0 = disable 1 = enable 6 EN_CLK7 0 enable signal output CLK7 0 = disable 1 = enable 5 EN_CLK6 0 enable signal output CLK6 0 = disable 1 = enable 4 EN_CLK5 0 enable signal output CLK5 0 = disable 1 = enable 3 EN_CLK4 0 enable signal output CLK4 0 = disable 1 = enable 2 EN_CLK3 0 enable signal output CLK3 0 = disable 1 = enable 1 EN_CLK2 0 enable signal output CLK2 0 = disable 1 = enable 0 EN_CLK1 0 enable signal output CLK1 0 = disable 1 = enable Register A9h TG config 10 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION REFER TO R171 (ABh) TG config 12 7 SEL_CLK3 0 select signal for CLK3 0 = output clock 1 = output pulse (select by SEL_PCK3[2:0]) 6:4 SEL_PCK3[2:0] 000 select pulse assigned to CLK3 (valid only when SEL_CLK3=1) 000 = PO0 001 = PO1 010 = PO2 011 = PO3 100 = PO4 101 = PO5 |
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