RT2702 datasheet(14/20 Pages) RICHTEK

14 / 20 page

RT2702

www.richtek.com

DS2702-00 October 2016

is a registered trademark of Richtek Technology Corporation.

Soft-Start

The RT2702 provides both internal soft-start function and

external soft-start function. The soft-start function is

implemented to prevent large inrush current and output

voltage overshoot during the start-up procedure. The soft-

start function automatically begins once the chip is

enabled. VFB will follow neither internal nor external soft-

start voltage ramp, depends on which ramp has lower

voltage. Since VDRV also has soft-start ramp, thus VFB

will begin ramping up after 3ms to 4ms from EN high.

As the region1 shown in the Figure 2, since external ramp

is quicker and higher than internal ramp, thus VFB follows

internal ramp during soft-start procedure. VFB will no longer

follow internal ramp when it is close to VREF, which is

0.6V, and sticks to the VREF. The internal soft-start time

is designed as a typical value 3ms from 10% to 90% VREF.

Soft-start procedure is finished after internal ramp rises

above 1.2V, in the meantime, int. SSOK will be asserted

high, and POK can be asserted high if OVP and UVP are

not triggered.

As the region2 shown in the Figure 2, because external

ramp is slower and lower than internal ramp, thus VFB

tracks external ramp during soft-start procedure. The

behavior is similar to region1 except that soft-start time

period is programmed. Note that SS pin would be left

floating after both int. and ext. SSOK are asserted high to

avoid SS pin having further disturbance to the loop. The

function block diagram of SS pin is shown in Figure 3

below. The RT2702 starts sourcing 10

μAtoward CSS which

is connected to SS pin. SS pin would be discharged when

system shuts down or re-starts up.

The external soft-start time can be calculated as :

REF

SS_Ext.

10 A







Where VREF is 0.6V, and CSS is the external capacitor

placed between SS pin and GND.

Figure 3. Soft-Start Control Block.

As the region3 shown in the Figure 2, if system is enabled

with SS pin having residual voltage, then VFB follows

internal ramp in the beginning since the voltage of internal

ramp is lower than external ramp(VExt. > VInt.). Afterwards,

VFB begins to track external ramp when the voltage of

external ramp is lower than internal ramp(VExt. < VInt.).

POK

The POK pin is the output of an open-drain buffer, thus it

requires a pull-up resistor. POK goes high when soft-start

is finished and has no UVP nor OVP.

Current Limit

The RT2702 provides cycle-by-cycle current limit control

by comparing the CSEN voltage VCSEN and RCS voltage VCS

of DCR circuitry to determine the turn-on timing of PWM.

The current limit circuit employs a unique “valley” current

sensing algorithm as shown in Figure 4. If the magnitude

of the CSEN voltage signal of DCR circuitry is above the

current limit threshold, the PWM is not allowed to initiate

a new cycle. Thus, the current to the load exceeds the

average output inductor current. Eventually, output drops

lower than the under-voltage protection threshold, inducing

IC shutdown.

To PWM Comparator

10µA

CSS

Control Logic

OTP

UV_Hiccups

Switch off if both

int. and ext. SSOK are high.

SS_Reset

Soft-Start Control Block

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