RT2702 datasheet(18/20 Pages) RICHTEK

18 / 20 page

RT2702

www.richtek.com

DS2702-00 October 2016

is a registered trademark of Richtek Technology Corporation.

PEAK

SOAR

OUT

)







where IPEAK is the peak inductor current.

Thermal Considerations

The junction temperature should never exceed the

absolute maximum junction temperature TJ(MAX), listed

under Absolute Maximum Ratings, to avoid permanent

damage to the device. The maximum allowable power

dissipation depends on the thermal resistance of the IC

package, the PCB layout, the rate of surrounding airflow,

and the difference between the junction and ambient

temperatures. The maximum power dissipation can be

calculated using the following formula :

PD(MAX) = (TJ(MAX)

− TA) / θJA

where TJ(MAX) is the maximum junction temperature, TAis

the ambient temperature, and

θJA is the junction-to-ambient

thermal resistance.

For continuous operation, the maximum operating junction

temperature indicated under Recommended Operating

Conditions is 125

°C. The junction-to-ambient thermal

resistance,

θJA, is highly package dependent. For a

WQFN-16L 3x3 package, the thermal resistance,

θJA, is

°C/W on a standard JEDEC 51-7 high effective-thermal-

conductivity four-layer test board. The maximum power

dissipation at TA = 25

°C can be calculated as below :

PD(MAX) = (125

°C − 25°C) / (30°C/W) = 3.33W for a

WQFN-16L 3x3 package

The maximum power dissipation depends on the operating

ambient temperature for the fixed TJ(MAX) and the thermal

resistance,

θJA. The derating curves in Figure 9 allows

the designer to see the effect of rising ambient temperature

on the maximum power dissipation.

0.0

0.4

0.8

1.2

1.6

2.0

2.4

2.8

3.2

3.6

4.0

100

125

Ambient Temperature (°C)

Four-Layer PCB

Figure 9. Derating Curve of Maximum Power Dissipation

Layout Considerations

Layout is very important in high frequency switching

converter design. If designed improperly, the PCB could

radiate excessive noise and contribute to converter

instability. Certain points must be considered before

starting a layout for the RT2702.



Connecting capacitors to VIN and VDRV are

recommended. Place these capacitors close to the IC.



Keep current limit setting network as close as possible

to the IC. Routing of the network should avoid coupling

to high voltage switching node.



Connections from the RT2702 to DrMOS should be as

short as possible to reduce stray inductance.



All sensitive analog traces and components such as

TON, EN, ILIM, SS, FB, CSN, CSP, POK, MODE,

PWM, DISB , THWN , GND and RGND should be

placed away from high voltage switching nodes such as

PHASE nodes to avoid coupling. Use internal layer(s)

as ground plane(s) and shield the feedback trace from

power traces and components.



Current sense connections must always be made using

Kelvin connections to ensure an accurate signal, with

the current limit resistor located at the device.



Power sections should connect directly to ground

plane(s) using multiple vias as required for current

handling (including the chip power ground connections).

Power components should be placed to minimize loops

and reduce losses.

Organic semiconductor capacitor(s) or specialty polymer

capacitor(s) are recommended.

The amount of overshoot due to stored inductor energy

can be calculated as :

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