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OPA838IDBVT Datasheet(PDF) 36 Page - Texas Instruments |
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OPA838IDBVT Datasheet(HTML) 36 Page - Texas Instruments |
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36 / 41 page ![]() Place bypass capacitors close to power pins Place input resistor close to pin 4 to minimize stray capacitance Place output resistors close to output pins to minimize parasitic capacitance Ground and power plane removed from inner layers Ground and power plane exist on inner layers 1 2 6 4 5 Place bypass capacitors close to power pins Remove GND and Power plane under pins 1 and 4 to minimize stray PCB capacitance Place feedback resistor on the bottom of PCB between pins 4 and 6 Power control (disable) pin Must be driven Non-inverting input terminated in 50 Ÿ 3 36 OPA838 SBOS867 – AUGUST 2017 www.ti.com Product Folder Links: OPA838 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated 11.2 Layout Example Figure 82. EVM Layout Example |
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